When the panel is in dead state, we early return from
the commit. So, the fences wouldn't be signalled till
the next Blank call. Handling this case by signalling
the outstanding fences when panel is in dead state.
Change-Id: I48a5e04707e32de0d1cdccf0592c981e30b618fc
Signed-off-by: Krishna Chaitanya Devarakonda <kdevarak@codeaurora.org>
In existing implementation on commit failure release fence are signaled.
But retire fence is not signaled. Which block the framework from
submitting next commit. And result in UI freez.
Add logic to signal retire fence along with release fence commit fails.
Change-Id: I84774280a110339450a1c5ef50eab68168e9bd20
Signed-off-by: Sachin Bhayare <sachin.bhayare@codeaurora.org>
Serialize wait for pingpong with kickoff when autorefresh
feature is enabled.
Change-Id: Ia51889dd86561e7513b4e7123a9fefb77a26d1ea
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
After part I authentication, SW DDC is not disabled and because of
this, we observe arbitration issues during part III authentication.
Disable SW DDC before starting part III of HDCP authentication.
Fail part II of authentication with repeater if its device count is zero.
Change-Id: I72f5b1115c094d4a72ae2b324f3903cdb195e5fe
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Extend HDCP1.4 SRM support for fb based hdmi driver as well.
Change-Id: I3d6597503d95b066d1fcfa71218cdda70965fbd0
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Extend HDCP2.2 SRM support for fb based hdmi driver as well.
Change-Id: I39bef2a814c2a2404a0a03584f23c58c69c10909
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Display Port driver never supported YC420 formats.
Also w.r.t to display quality, 4K30 RGB 8bit is
better than 4K60 YC420 8bit.
So, do not include edid modes(VICs) from YC420 Video
Data Block while parsing EDID.
Change-Id: I77f2c45c22beceb7f554a4c063f6e6947dc4ba8a
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Clear PP features dirty flags only when they are programmed, based on
programming stage, i.e. clear dirty flags of features programmed in
early stage after early stage programming and clear dirty flags of
features programmed in deferred stage after their actual programming
is complete.
Clearing the flags in one go is resulting in missing programming of
features designated to be programmed in early stage, if the dirty flags
are updated in between the stages.
Change-Id: If65a5982254a7421c6f0ec32018361c651964e4e
Signed-off-by: Ch Ganesh Kumar <chganesh@codeaurora.org>
Audio event is wrongly notified during pre_panel_off event.
Modify HDMI Audio event notification sequence so that audio
events are notified as expected.
CRs-Fixed: 2131442
Change-Id: I5fb5d28cb0162f0c4bf97e29556b15d12e1ea8f1
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Add changes to reset basic_audio_support parameter
before parsing EDID on every new cable connection.
Change-Id: I52fef059830d950d4858d5bee3f76774426e6863
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Current Display Port driver is incorrectly parsing sink count
register (0x200) of DPCD. Made changes to parse it correctly
as per DP specification.
Change-Id: Ic858485f19f226f7b2d84f74c97170db8bebf822
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Local variable in function should be initialized before using it.
Change-Id: I132033fa650cdacae3c8b2a98b8a593d159fe967
CRs-Fixed: 2202957
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
VREG was enabled during init and never turn off until the bridge chip
unregister. We need to add VREG on/off sequence into bridge chip
power on/off in order to reduce platform current draw.
Change-Id: Ib8d59665c55035c36d10d868fb256fcfaa243f84
Signed-off-by: Camus Wong <camusw@codeaurora.org>
Adding power off register sequence to reduce power in power off.
Adding switch GPIO sequence in power on/off call.
Change-Id: Ifbe57852a43e1b1d0f05594a84a10540cfeb6be7
Signed-off-by: Camus Wong <camusw@codeaurora.org>
The commit_in_progress flag is set only after waiting for the fences
in the current composition cycle. This will ensure that the
release fence of the previous composition is signalled, even though
there is a fence timeout in the current composition cycle.
Change-Id: I06653c922f195bb5936530ddeaa5a9fcb291fb3f
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Trigger an idle fallback with a reasonable timeout value when
there is no update despite of a touch event and idle_time is 0.
This will reset the refresh rate to minimum fps.
CRs-Fixed: 2003247
Change-Id: I4a2964038f23984bf1ea39c63bf679d80ad12cba
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
In current HDMI driver, SVDs and DTDs derived from EDID
of a DS HDMI sink are checked for supportness based
on previous connection's max TMDS clock.
Always reset the max TMDS clock supported by source
before reading EDID from DS HDMI device.
Change-Id: If5f58562f186634b1ed066fdebfc9fa6b55c6e8a
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Clear the deep color bits in the HDMI controller in case
the mode does not need OR support deep color.
Change-Id: I77a5cd74bc90c249d8902437a7b87a07259a2c35
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Parameter mdss_mdp_plane_sizes must be cleared to 0 before returning
under an error condition, otherwise caller function will use the
uninitialized mdss_mdp_plane_sizes values and caused incorrect
operation.
Change-Id: I856b17ce9e917cc450040463ec34b7309d34b9b5
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
Fix the programming of DisplayPort SDP registers primarily related
to Audio enable sequence. This would fix potential issues caused by
read/append/write operations on SDP registers which might corrupt
the parity/data bytes. This would lead to audio issues since the DP
controller would treat the corrupt SDP information as invalid data.
Change-Id: I55db6a70be0fdf94a60fd7cc8bf0d30702febef8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Do not need to do HDMI PHY reset here, because will do
that when HDMI cable connected again in HDMI mode setting
function.
Change-Id: Ifae7c35f72a9008980c207e0806ab7aaa57dfe07
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Dsi controller v2.1 and above supports scheduling of dma
commands. Schedule dsi cmds at the starting of blanking
region to avoid sending of commands in active region
resulting in dsi overflow errors.
Change-Id: I658b7d7008eb9071148820c0ea949ae9ba593ed9
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
The NVID programming for Display Port needs to be set to twice
the 'n' divider of the pixel clock RCG for 5.4 GHz link rate.
Add change to take care of this in Display Port driver.
Change-Id: Ied31f67372d9738e96d1d908acd96a02b82d4630
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
The DP VCO divided mux clock has two parent dividers div_two
and div_four. The parent for this needs to be set based on the
link rate frequency as per the hardware programming guide and
not based on the auto PLL calculation logic. Add support to set
the correct parent for this.
Change-Id: Ia2d340a4e8790d90161c1f4a7c8273449fa3f53c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
In the current implementation before triggering ESD read,
DSI SW waits for extra time to skip display blanking period.
Add an additional check for active line count to ensure that
ESD read is always triggered during display active region only.
Change-Id: I5893daf7cdfb8c1d0a0e962eb2e37d7cd053a6a5
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
HDCP1x module is initialized only if HDCP 2.2 is not present either from
the source OR sink side. Make sure to call the HDCP 1x APIs only if
HDCP 2.2 is not present. Otherwise this leads to a crash.
Change-Id: Id66dec10ffd585630a2e4c1e5c75bee99ce515de
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
HDCP driver provides a common interface for both Display port
and HDMI clients. As HPD IRQ enable API is valid only display
Port, make sure it is handled gracefully when called
from HDMI client so that invalid resource access can be avoided.
Change-Id: I42e07c6019300b37ea3426347fef571bbb6e278c
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
If DP cable is disconnected while processing HPD or IRQ_HPD,
DP driver may continue with failsafe parameters and notify
connection event and immediately notify disconnection event
which may result in state machine corruption in userspace.
Add changes to avoid reading dpcd caps, edid, link training
or connection events if DP cable is disconnected in between.
Change-Id: I0b59ebdb636c9dc1086673253399b849734d51ee
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
When the source is powered off with an external sink connected, it
will result in a call to blank and power off the source. In the
current implementation, sink is not transitioned to D3 power mode
prior to turning off the source. This can result in the sink
reporting signal lock failures as the source if powered off,
resulting in an HPD IRQ interrupt. If this interrupt is handled
after the DP controller is powered off, it can lead to unclocked
register accesses. Fix this by ensuring that sink is powered off
prior to powering off the source. In addition, ensure that no more
attention events are handled once the DP controller is powered off.
Change-Id: I08558229f7c3e603904527de58a39039b3d7615e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
PLL_ENABLE property is used to enable or disable the PLL
update function. With this property PLL update function
only works when PLL_ENABLE is set, and all changes done
to hardware will be discarded once PLL_ENABLE is cleared.
Change-Id: I4a6173de22285b37df1b9371ad29e634ef076edc
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Secure display entry/exit should be accompanied
by null commit in video mode to make sure there is
no non secure access.
Change-Id: I7928a2465de9c46f69e963977931f7a6618f01fb
Signed-off-by: Animesh Kishore <animeshk@codeaurora.org>
HDR playback needs metadata to be sent to the sink
while the playback is ongoing and needs a proper
teardown sequence when the playback has ended with respect
to the infoframe being sent to the sink.
This needs a state machine to synchronize start/stop of
the playback with sending the right metadata along with
resetting the infoframe HDMI registers.
Add support for this HDR playback control state machine.
Change-Id: I58ff03bc8db99febd17e0a0853acc74668892ea8
Signed-off-by: Ch Ganesh Kumar <chganesh@codeaurora.org>
dchdr->dlen is a short variable controlled by the user-provided data
(a string). If the value is negative, the condition does not pass
and loop continues, also increasing the value of "len". As a result
buffer overflow and overwrite occurs.
Change-Id: I5eacec446c9a8b5b82fc3bc6d1281303f336d4de
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
