Add a DT property to specify DP PHY register offset for display
port. There is a register offset difference for a few DP PHY
registers between msm8998 and SDM660 and hence this is needed.
Add changes to program DP PHY registers by accounting for this
register offset difference wherever applicable.
Change-Id: I515432830ae6c3fa3223f0c97af7b0a3965afc40
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Display port settings for logical to physical lane mapping and AUX
configurations are different between msm8998 and SDM660. Add support
to parse these settings from MDSS DT file. Add the relevant settings
for the same in msm8998 MDSS device tree node.
Change-Id: I5046b2523928e34ef42924f495dfc754d9ac6ea7
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
IBB discharge resistor configuration needs to be decided on the
mode (LCD/AMOLED) along with the capacitor used on the hardware
platform. On hardware platforms that uses pmi8998, this would be
configured in the bootloader and HLOS should not be modifying it
based on the mode.
Hence, remove the property in msm-pmi8998.dtsi. Change the device
tree property to optional so that the driver can probe even when
the property is not specified.
Also, remove the code that force discharge resistor configuration
to 300KOhms for AMOLED mode as it can be done either in the
bootloader or through device tree.
CRs-Fixed: 1115531
Change-Id: I0da5db166bb99a732978c287e97566f649686f42
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Core clock rate can be reduced or increased based on operating
speeds. Controller starts in Super Speed mode (higher core clock
rate) and it will operate in super or high or full or low speed
upon device connection. Update the core clock rate based on bus
speed to allows system to operate in better low power state (such
as SVS1/SVS2 based on system configuration). High Speed rate for
core clock is programmed from dtsi. Super Speed rate will be used
if High speed core clock rate is not provided for backward
compatibility.
Change-Id: I265149d34de19ab50bd7f106a670a7112bfae384
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
commit 2e575cbc930901718cc18e084566ecbb9a4b5ebb upstream.
The type of AVIC interrupt controller found on i.MX31 is one-cell,
namely 31 for CCM DVFS and 53 for CCM, however for clock control
module its interrupts are specified as 3-cells, fix it.
Fixes: ef0e4a606f ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This reverts 'commit 54a4a3fb41 ("drm/msm/sde: add
driver for sde support")'
This is partial change for display drm driver,
that will break drm/sde merge commit.
Change-Id: Iea6b08608a30979232826efba8fbb2a631d93f83
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Model and configure MDSS Display Port PLL for SDM660 target.
Add changes to define and register DP VCO, divider and mux clocks
as per common clock infrastructure.
Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Add support for configuring the memory accelerator (MEM-ACC)
threshold voltage for the Silver cluster. This threshold
voltage is used to resolve the MEM-ACC crossover virtual corner
number required by the OSM sequence to program MEM-ACC settings
based on a voltage threshold.
CRs-Fixed: 1113780
Change-Id: Iba58a23ae0d30429da629afa9d5f9cb34e025543
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support to Enable/Disable uc monitor holb feature.
sdm660 does not support uc monitor holb feature.
Make changes to get this param via device tree to
support devices which handle holb monitoring via IPA uC.
sdm660 supports WLAN offload. Make changes to configure
wlan pipes on IPA2.6L needed to support WLAN offload.
Change-Id: I07e099ffb7833e4790dda1fd4864f3f61acb2a45
Acked-by: Mohammed Javid <mjavid@qti.qualcomm.com>
Signed-off-by: Utkarsh Saxena <usaxena@codeaurora.org>
Bus clocks are managed via bus apis and hence move to using them for
enabling bus clocks. The previous method could enable a bus clock at a
higher than required frequency, wasting power.
The power on sequence is regulator on, bus vote, and then enable
remaining clocks.
Remove all clocks which are of RPM_SMD type (including mmssnoc_axi_clk)
since these are managed by the bus driver. Using an active-only bus vote
instead should save power when APPS is power collapsed.
Keep the mmss_mnoc_ahb_clk because it is a branch clock type which is
not managed by the bus driver. No active-only mode is available for this
clock.
Change-Id: I3b35d81098b8bd5299b27e85d27aa959e7cf415a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm8998 supports 10bit csc while msm8996 supports csc only.
This patch adds the dtsi entry to select the correct csc
type while parsing hardware catalog to configure the
valid csc hardware block.
Change-Id: I376f1e485a5de4a95d03e395e06d10b043036cb0
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Snapshot of low persistence mode changes as of
26cfe58bd94a ("msm: mdss: Add support for low persistence
display mode") and a805a3e1e791 ("arm64/dts: angler: Don't
blank screen when leaving low persistence mode"), to add
low persistence mode support for display. Also, add some
changes to optimize the implementation for LP mode and
fix crash issue when VR APP is up.
CRs-Fixed: 1104888 1108207
Change-Id: I509fb5c87d93e2416882942a226cb9b48bc1d3bf
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
Add playback and capture support when an analog wired
accessory is inserted into USB Type-C receptacle through
an USB type-c to 3.5mm analog audio adapter.
CRs-Fixed: 1102048
Change-Id: I36126ecdb0d2683d27d78dea9256bee0be67c1a6
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
External sense configuration is not supported. Hence remove it.
Change-Id: If65eb8c4d9720d4c4e9d913c91c8b33f420f29d1
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
The power directory structure has changed in kernel version 4.9. Align
msm-4.4 with this new directory structure.
Change-Id: Iba729f8ef33245ea78cdc05276ba8f5593191509
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add device tree support for QRD630 EVT2 SKU1 board.
Change-Id: I8cea2b9b0995905297d69951694178dccfea65f7
Signed-off-by: Jiangen Jiao <jiangenj@codeaurora.org>
Select which SPSS firmware to load based on 2 fuses.
Change-Id: I7080cc0b58c38965ed7e58808431cf487008de9e
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
When VCONN is enabled while OTG is disabled the CC line which is not
configured for VCONN can be internally pulled down. If the Type-C plug
were removed then Type-C detection would still see that Rd is applied and
not detect the removal.
Fix this by ensuring that OTG is enabled while VCONN is enabled. If OTG
were disabled due to an over-current event then VCONN must also be
disabled.
Implement a retry mechanism if over-current is detected on either VCONN or
VBUS.
Change-Id: Iccfb923bce8f06c7c1270943211ce134ea9ef616
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
GPU RBCPR clocks needs to registered separately, as GFX CPR would require
the rbcpr clocks to register the regulator handle.
Change-Id: I59def76e7dd69600be8faf47eb867a97ab04739e
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Some platforms may use external gpio to enable and disable backlight,
and we may need to invert this gpio according to HW design,
so add support for that.
CRs-Fixed: 1109294
Change-Id: Ib5e895eebcc38d185e8b703c3d895781b43c58c7
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
Set moisture threshold values depending on the HW
configuration for NO Jack.
CRs-Fixed: 1099543
Change-Id: If995d462f1aeffb443471580520b1c8b5abca811
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
sdm660 CPU CPR controllers support full hardware closed-loop CPR
operation also known as CPR hardening. Extend the cprh-kbss-regulator
driver to handle CPU subsystem specific power requirements of
the sdm660 chip.
CRs-Fixed: 1105923
Change-Id: I2e24a061a5ad4ee959dd578da9e811ac7700702c
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
As per the hardware documentation, add support for configuring
ESR tight and broad filters for normal and low temperature. This
is needed as the low temperature ESR filter coefficients are not
functional in the hardware.
All the filter values (in terms of percentage) can be configured
through the device tree. When the battery temperature goes below
10 C or user configured temperature threshold, ESR filter values
of room temperature will be applied to ESR low temperature
filters. Once the battery temperature goes above 10 C, original
values will be applied back to ESR low temperature filters.
Change-Id: I347f194f96ace3036a3c49efe0306d9f909cef36
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Provide the support to enable MCLK output to external
audio connections. Also, update configuration to set
bit clock as EBIT in slave mode.
CRs-Fixed: 1094763
Change-Id: If07f31a6c37c7b8b23eb74b25a1e15990043cb92
Signed-off-by: Tanya Dixit <tdixit@codeaurora.org>
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
