Use nominal ahb clock value while loading firmware to speedup the
firmware load process. Vote to SVS once firmware loading is done.
CRs-Fixed: 1077224
Change-Id: I8518d349a7838f9600e32d5b2a5853f7f96f9008
Signed-off-by: Krishnankutty Kolathappilly <kkolatha@codeaurora.org>
The post vco divider clock in the DSI PLL can only be configured
to a fixed value of 1 or 4. Current implementation can result in
the divider being set to any value between 1 and 4 which can
result in failures while enabling the DSI pixel clock. Fix this
by replacing the post vco divider with a fixed /1 and /4 dividers
followed by a mux clock.
CRs-Fixed: 1064277
Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Initliaze the local variables that are used in functions to return
success or error codes. This fixes possible cases where undefined
error codes are returned.
CRs-Fixed: 1070186
Change-Id: I74bed6cfd9753765b15d17d69ba30f61875e87c8
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
Use vars in driver context after proper initialization
Change-Id: I3e59e27534b8e1088d74b42c72e0075d2fe910e6
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
CRs-Fixed: 1049521, 1049615
During subsystem restart, the codec hardware goes through reset. Add
support in the wcd934x dsp controller driver to handle codec reset
and perform necessary reset of the codec dsp.
Change-Id: I9916354c04e24708aced5fc63bc12ddfe87b49f2
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
During medium and high discharging scenario, voltage mode
correction needs to be applied so that the battery SOC can
follow closely with the battery voltage. Add support for this
by configuring the ki coefficients for medium and high discharge
current during discharging.
Change-Id: I0a76e9e2f74c40b55e01f9dc106d31a148edefdf
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
There is a requirement to show battery SOC at 100 when charging
status reaches full as long as the charger is connected and SOC
doesn't drop below automatic recharge threshold. Add support for
this through a device tree property "qcom,hold-soc-while-full".
Also, when charging status reaches full, recharge SOC threshold
need to be adjusted depending on the SOC where termination
happens. This will be more prominent in jeita conditions. Add
support for it.
Change-Id: Icc9536f17eedc3559c9f70dc2a8b73127c78c98a
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
C-state aware scheduler takes note of wakeup latency of each c-state
level to determine whether to pack or wake up LPM CPU. But it doesn't
distinguish small and large delta as it's inefficient for scheduler to
do so on its critical path.
Disregard wakeup latencies less than 64 us between different c-state
levels. This reduces unnecessary task packing.
CRs-fixed: 1074879
Change-Id: Ib0cadbd390d1a0b6da3e39c98010cedb43e5bf60
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
C-state aware scheduler at present, uses a raw c-state index number as
its determinant and avoids task placement on deeper c-state CPUs at
cost of latency. However there are CPUs offering comparable wake-up
latency at different c-state levels and the wake-up latency at each
c-state levels are already have being fed to scheduler.
Hence use the wakeup_latency as c-state determinant instead of raw
c-state index to avoid unnecessary task packing where it's doable.
CRs-fixed: 1074879
Change-Id: If927f84f6c8ba719716d99669e5d1f1b19aaacbe
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
These configs are required to enable new tunable functionality in
the scheduler.
Change-Id: I94ef9c913e1d5be2801d553fdc859b80b62e8aa5
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
The check for NULL css is redundant as upper layers are already
making sure that css cannot be NULL. Remove this check. It helps
to silence static analysis errors as well.
Change-Id: I64585ff8cceb307904e20ff788e52eb05c000e1f
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Update the FMAXes for the dp_pixel_clk_src RCG on MSMCOBALT
to match the HW recommendations.
Change-Id: I781a68db35f90ba3e89da8a9cd6cf4ebdfbb0eb3
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Change over to using outer shareable for both coherent and
non-coherent page tables and for both coherent and non-coherent
data buffers.
This is done to be more in line with the ARM spec.
Change-Id: Icebf88641a5ebb82bb4b7577d1ab402580b1460c
Signed-off-by: Liam Mark <lmark@codeaurora.org>
This reverts commit b97da4469b ("net: Warn for cloned packets in
ingress path on SMP systems only") and commit e1f88edd76 ("net:
Warn for cloned packets in ingress path"). The path for GRO is well
tested now and cannot receive cloned packets. Loopback packets are
triggering this warning leading to a false positive.
CRs-Fixed: 1077079
Change-Id: I8f36906f508998c6369f30e0eadc1703c70533b9
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
It is recommended to ensure that the interface timing engine is on
when configuring the hardware to switch to "IDLE pattern" state
as part of the shutdown sequence. In addition, it is also preferred
to issue a global software reset of the controller to ensure that
it's state machine is reset for any subsequent connections.
This updated sequence fixes link training failures seen during
multiple connect/disconnect use-cases.
Change-Id: I1984c1fc8c3e4a5f9c818240ec7e0323a68bfe3b
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Keeper enable bit is used to reduce the current leakage
from soundwire master. Enable this bit before starting
audio use-case through soundwire and disable once
use-case is completed.
Change-Id: If2dc9e7fd9a2710391d02c0e52a291b3cffc63b6
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Remove msm_bus bandwidth vote as WLAN FW will take care of it.
CRs-Fixed: 1075319
Change-Id: I618cc3603df6af18409613209e0373d7e36202fd
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Add support of reading the status of the device, parsing it and
sending it to the Input framework using the input APIs.
Change-Id: Iebc3767e9dbcf10a541b8b02f8696da84312447a
Signed-off-by: Vevek Venkatesan <vevekv@codeaurora.org>
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
As read/write get access to ion memory region as well, it's
necessary to lock them when ion memory is about to be added/freed
to avoid racing cases.
CRs-Fixed: 1071809
Change-Id: I436ead23c93384961b38ca99b9312a40c50ad03a
Signed-off-by: Walter Yang <yandongy@codeaurora.org>
For SDCC version 5.0.0, MCI registers are
removed from SDCC interface and some registers
are moved to HC. This change is to support MCI
register removal for msmfalcon.
New compatible string "qcom,sdhci-msm-v5" is
added for msmfalcon to support this change.
Change-Id: I9a972c5656762385f11214fe22398cc14a996d29
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
Some sinks expect configure command before notifying hpd
as high in status or attention command. Do not wait for
hpd to go high to send configure command to sink. Once the
configure command has been sent to sink, sink may send attention
command back to source with hpd high. Configure source power on
if attention command is received with hpd high.
Change-Id: Ic5254da65f3720a8313881bc419ec912a0ed6997
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update diag header with new MSG SSID for DPM.
CRs-Fixed: 1076696
Change-Id: I681509b653c419159f6ca4172c5ff66a1cae1b79
Signed-off-by: Chris Lew <clew@codeaurora.org>
Current register settings for memory control allow only few memory
banks to enter deep sleep. This could cause some of the memory banks
to not enter deep sleep mode, resulting into higher power consumption.
Fix the register sequence to make sure the memories are allowed to
enter deep sleep mode.
Change-Id: I2ae0fe35e9a207b33f88077ca6ec49d593d43b68
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
It is possible that codec hardware can be reset in case of subsystem
restart scenarios. It is required to reset the codec DSP as well in
such cases to make sure the DSP is in usable state after the codec
hardware is reset. Change adds support to handle codec down and up
events and perform the necessary reset on codec DSP.
Change-Id: I79502c043f5e16947c895aab7cd584d72ad1a7dc
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
The wdsp_intr_handler is not really processing interrupts in interrupt
context, rather assumes that the caller is not in interrupt context and
performs calls that may sleep. Rename the function in order to avoid
confusion. Interrupt handlers can still call this function as long as
they are in threaded interrupt context and are okay to sleep.
Change-Id: Ia2803d6ca021d505ed2e711e676cbd701b11c492
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
One time initializations like regmap and debugfs init are currently
done in the init function. But, in case of subsystem restart, the
driver can get de-initialized and then initialized again. This causes
the debugfs and regmap entries to get removed and added again during
subsystem restart cases. Avoid this by moving all the one time
initialization of the driver to component bind.
Change-Id: Ideed297fde016b0623616be64875be094e688981
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
Initialize variable to default value before
it is used so that variable does not print
uninitialized value in debug logs.
CRs-Fixed: 1059495
Change-Id: Ic7ed961d8beb16eee35414825ec6ba7d4e95a60d
Signed-off-by: Vikram Panduranga <vpandura@codeaurora.org>
