i.MX6DL does not have the second IPU, but the LVDS multiplexers can connect
either LVDS channel of the LDB to IPU1 DI0 or IPU1 DI1.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: remove "crtcs" property from imx6qdl.dtsi]
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch enables the On-Chip SRAM (OCRAM) on i.MX53 and i.MX6 SoCs.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Board files for Phytec phyCARD-S "System on Module" and "Rapid
Development Kit".
Based on patches from:
Steffen Trumtrar <s.trumtrar@pengutronix.de>:
- Original patch
- ARM: dts: Set partition offsets for phycard
- ARM: dts: Use CSPI1 instead of CSPI2 on phycard pca100
- ARM: imx27-phytec-phycard-S.dts: resize nand partitions
Jan Luebbe <jlu@pengutronix.de>:
- ARM: dts: Enable bad block table in NAND
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Set operating-points for imx27. There is no regulator support, so the
voltages are 0. The frequencies should be the same for all imx27 boards,
so it is defined here and can be overwritten if necessary.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On the MX27 Reference Manual the interrupt controller is named AITC:
ARM926EJ-S Interrupt Controller
So use the AITC term instead of AVIC.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Origin: id:1334193132-18944-2-git-send-email-festevam@gmail.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The mc13892 driver knows that it needs spi-cs-high, so the mc13892
will work. The dataflash also connected to this bus though can only
be probed when the mc13892 is inactive. Due to driver potential
differences in the probe order we can only make sure the mc13892
is inactive when we put the information into the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For keeping the alphabetical order in the pinmux nodes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 gpt is handled by the i.MX31 gpt driver in the kernel,
so add a corresponding compatible entry.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6Q and i.MX6DL are pin compatible, so the pinmux entries
should be in sync. This patch systematically adds the pinmux entries
missing from the imx6q to the imx6dl file.
Some name inconsistencies and whitespace damage is fixed along the
way.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Define minimal memory layout for i.MX27 PCM-038 module.
This will help to use appended DTB with non-DT capable bootloaders.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
i.MX27 have only one PWM, so index from PWM devicetree node removed.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds the missing (Symmetric/Asymmetric Hashing and Random
Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- update codec, pmic, usb hub for Arndale
- add exynos4412-trats 2 board dt
- update camera, spi, sensor for Trats2
- update fimc, sensor for Trats
- add support tmu for exynos5440
- add support g2d for exynos5250
- correct camera pinctrl for exynos4x12
- add support camera subsystem for exynos4
- add support basic pm domain, fimd, dp for exynos5420
- add support secure-firmware for OrigenQuad
- update mfc and add support mfc for exynos5420
- add usb host node for exynos4
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Merge tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
Samsung Exynos DT updates for v3.12
- update codec, pmic, usb hub for Arndale
- add exynos4412-trats 2 board dt
- update camera, spi, sensor for Trats2
- update fimc, sensor for Trats
- add support tmu for exynos5440
- add support g2d for exynos5250
- correct camera pinctrl for exynos4x12
- add support camera subsystem for exynos4
- add support basic pm domain, fimd, dp for exynos5420
- add support secure-firmware for OrigenQuad
- update mfc and add support mfc for exynos5420
- add usb host node for exynos4
* tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (38 commits)
ARM: dts: Add USB host node for Exynos4
ARM: dts: add audio clock controller for exynos5420
ARM: dts: Correct the /include entry on exynos5420 dtsi file
ARM: dts: Add MFC node for exynos 5420
ARM: dts: Update 5250 MFC node
ARM: dts: Remove unsused MFC clock from exynos4
ARM: dts: Update clocks entry in MFC binding documentation
ARM: dts: Hook up internal PHY on Arndale
ARM: dts: Enable USB hub on Arndale
ARM: dts: Add secure-firmware boot support for OrigenQaud board
ARM: dts: Add pin state information for DP HPD support to Exynos5420
ARM: dts: Add DP controller DT node to exynos5420 SoC
ARM: dts: Update DP controller DT Node for Exynos5 based SoCs
ARM: dts: Add FIMD DT node to exynos5420 DTS files
ARM: dts: Add basic PM domains for EXYNOS5420
ARM: dts: Update FIMD DT node for Exynos5 SoCs
ARM: dts: Move display-timing information inside FIMD DT node for exynos5250
ARM: dts: Add S5K5BA sensor regulator definitions for Trats board
ARM: dts: Add Exynos4210 SoC camera port pinctrl nodes
ARM: dts: Add FIMC nodes for Exynos4210 Trats board
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This fixes a regression exposed during the merge window by commit
9f310de "ARM: tegra: fix VBUS regulator GPIO polarity in DT"; namely that
USB VBUS doesn't get turned on, so USB devices are not detected. This
affects the internal USB port on TrimSlice (i.e. the USB->SATA bridge, to
which the SSD is connected) and the external port(s) on Seaboard/
Springbank and Whistler.
The Tegra DT as written in v3.11 allows two paths to enable USB VBUS:
1) Via the legacy DT binding for the USB controller; it can directly
acquire a VBUS GPIO and activate it.
2) Via a regulator for VBUS, which is referenced by the new DT binding
for the USB controller.
Those two methods both use the same GPIO, and hence whichever of the
USB controller and regulator gets probed first ends up owning the GPIO.
In practice, the USB driver only supports path (1) above, since the
patches to support the new USB binding are not present until v3.12:-(
In practice, the regulator ends up being probed first and owning the
GPIO. Since nothing enables the regulator (the USB driver code is not
yet present), the regulator ends up being turned off. This originally
caused no problem, because the polarity in the regulator definition was
incorrect, so attempting to turn off the regulator actually turned it
on, and everything worked:-(
However, when testing the new USB driver code in v3.12, I noticed the
incorrect polarity and fixed it in commit 9f310de "ARM: tegra: fix VBUS
regulator GPIO polarity in DT". In the context of v3.11, this patch then
caused the USB VBUS to actually turn off, which broke USB ports with VBUS
control. I got this patch included in v3.11-rc1 since it fixed a bug in
device tree (incorrect polarity specification), and hence was suitable to
be included early in the rc series. I evidently did not test the patch at
all, or correctly, in the context of v3.11, and hence did not notice the
issue that I have explained above:-(
Fix this by making the USB VBUS regulators always enabled. This way, if
the regulator owns the GPIO, it will always be turned on, even if there
is no USB driver code to request the regulator be turned on. Even
ignoring this bug, this is a reasonable way to configure the HW anyway.
If this patch is applied to v3.11, it will cause a couple pretty trivial
conflicts in tegra20-{trimslice,seaboard}.dts when creating v3.12, since
the context right above the added lines changed in patches destined for
v3.12.
Reported-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The Cubieboard2 is the successor of the first Cubieboard, and shares the
same hardware, except that the Allwinner A10 found initially has been
replaced by an Allwinner A20.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20-olinuxino Micro has a LED connected to the PH2 pin. Use the
gpio-led driver to enable the control over this LED.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Instead of relying on the bootloader to mux the UART pins properly, do
it on our own and register the rightful pins for the A20-olinuxino in
the DT using pinctrl.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The UARTs on the A20 can be muxed to several pins. Add a few options to
the DTSI so that we can start using them in the boards' DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO controller is responsible for the GPIO/muxing/external
interrupts handling. Now that we have support for the A20 pin set in the
pinctrl driver, we can start using it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Cleanups and few fixes to the DTSI
- A few additions to the A10s olinuxino board
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Merge tag 'sunxi-dt-for-3.12' of https://github.com/mripard/linux into next/dt
Allwinner sunXi DT additions for 3.12
- Cleanups and few fixes to the DTSI
- A few additions to the A10s olinuxino board
* tag 'sunxi-dt-for-3.12' of https://github.com/mripard/linux:
ARM: sunxi: dt: Add device tree for Mele A1000
ARM: sun5i: dt: Fix A13 SoC bus base address
ARM: sun5i: a13: Remove useless simple-bus reg property
ARM: sun5i: dt: Fix A10s SoC bus base address
ARM: sun5i: a10s: Remove useless simple-bus reg property
ARM: sun4i: dt: Fix A10 SoC bus base address
ARM: sun4i: a10: Remove useless simple-bus reg property
ARM: sunxi: make the leds' names conform to the current naming convention
ARM: sun5i: dt: Add AT24 device on A10S-OLinuXino-Micro
ARM: sun5i: dt: Enable I2C controllers on A10S-OLinuXino-Micro
ARM: sun5i: dt: Add I2C controller nodes to the A10S dtsi
ARM: sun5i: dt: Add I2C muxings for sun5i A10S
Signed-off-by: Kevin Hilman <khilman@linaro.org>
DT kernel on da850-evm comes up with garbled UART logs. This is because
of mismatch in actual module clock rate and rate specified(clock-frequency)
in DT blob. kernel should not assume or depend on bootloaders clock
configuration, instead let it find the clock rate at runtime.
Issue discussed here before arriving on this implementation:
"ARM: davinci: da850 evm: update clock rate for UART 1/2 DT nodes"
https://patchwork.kernel.org/patch/2162271/
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add ethernet device tree node information and pinmux for mii to da850 by
providing interrupt details and local mac address.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
