At the end of pulse train ESR measurement is forced. It is expected
that when ESR is being measured, which takes about 1.5 seconds, the
next pulse train does not start.
However we see that a uevent is sent to userspace and it enables pulse
train within 100mS.
To prevent that put the pulse train enabling bit under a votable
control. And make QNI_VOTER (the userspace voter) and ESR_VOTER vote
on it.
Moreover, the current pulse train enabling path checks if qnovo was
enabled, make a QNOVO_OVERALL_ENABLE voter to this new voter to reflect
it.
Change-Id: I6d2177250cc47f5aeb6591c532ee18d37e3b02c6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
When FG IADC measurement period coincides with qnovo discharge pulses
it reads incorrect IADC values. That causes issues with SOC accuracy
and capacity learning amongst others.
The fix to IADC inaccuracy is to set a bit in the FG
peripheral while Qnovo is active.
A side effect of IADC inaccuracy fix is that the ESR
measurement goes haywire. To overcome that, disable ESR when
Qnovo is active and force an esr measurement when its between pulses.
Realize this by disabling ESR and enabling the bit when
Qnovo becomes active. The qnovo driver will set CHARGE_QNOVO_ENABLE
property on the bms psy when its active. Also provide code to
force an ESR measurement via a write to RESISTANCE property in
bms psy.
Change-Id: I7160ad6288362c17d28d67b38ec09332d9a6cbd2
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
When FG IADC measurement period coincides with qnovo discharge pulses
it reads incorrect IADC values. That causes issues with SOC accuracy
and capacity learning amongst others.
The fix to IADC inaccuracy is to set a bit in the FG peripheral while
Qnovo is active.
A side effect of IADC inaccuracy fix is that the ESR measurement goes
haywire. To overcome that, disable ESR when Qnovo is active and force
an esr measurement when its between pulses.
Realize this by setting CHARGE_QNOVO_ENABLE and RESISTANCE property on
the bms psy at appropriate times in the driver.
Change-Id: I5b37083c843ec6bc052c4d344347b9a80554e226
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
When transfer buffer is larger than available space, uci driver will
split the transfer into multiple transactions. Driver incorrectly
calculated the transfer length and caused infinite transfer.
Simplify uci write method to avoid such bugs.
CRs-Fixed: 2083693
Change-Id: Ic7169cefda6a4637511ecfa3ce5ddde6f3d55f8c
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
If a spinner is present, there is a chance that the load of
rwsem_has_spinner() in rwsem_wake() can be reordered with
respect to decrement of rwsem count in __up_write() leading
to wakeup being missed.
spinning writer up_write caller
--------------- -----------------------
[S] osq_unlock() [L] osq
spin_lock(wait_lock)
sem->count=0xFFFFFFFF00000001
+0xFFFFFFFF00000000
count=sem->count
MB
sem->count=0xFFFFFFFE00000001
-0xFFFFFFFF00000001
RMB
spin_trylock(wait_lock)
return
rwsem_try_write_lock(count)
spin_unlock(wait_lock)
schedule()
Reordering of atomic_long_sub_return_release() in __up_write()
and rwsem_has_spinner() in rwsem_wake() can cause missing of
wakeup in up_write() context. In spinning writer, sem->count
and local variable count is 0XFFFFFFFE00000001. It would result
in rwsem_try_write_lock() failing to acquire rwsem and spinning
writer going to sleep in rwsem_down_write_failed().
The smp_rmb() will make sure that the spinner state is
consulted after sem->count is updated in up_write context.
Change-Id: I96de9a65adedb35d1ee2c6c36dc7759c9b8f5d4d
Signed-off-by: Prateek Sood <prsood@codeaurora.org>
The patch frees the read workqueue structure after
scheduled workqueue processes the glink buffers and notifies
glink to avoid possible memory leak.
CRs-Fixed: 2083447
Change-Id: I4e562f9d1cbf02d8306e0a127835af85dfa5db23
Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
Currently, flushing of control workqueue is happening
under protection which is causing a deadlock. The patch
fixes the issue by flushing the control workqueue on
immediate closure of channel.
CRs-Fixed: 2081948
Change-Id: I6a7b1ee7cbabf2974700e28fc62c6d8fa3d464ed
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
Currently, memshare allocates 5MB memory to diag client on
receiving requests from modem. With the patch diag client
will be considered guaranteed on sdm630 to avoid memory
allocation failure on modem SSRs. Also being guaranteed
client allocated memory will never be freed.
CRs-Fixed: 2054448
Change-Id: I7b0780d064a27e8ebca9d31747ce1f9c18d84fdb
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
In offline charging mode, modem is not loaded so the proxy
IPA clock vote added by IPA driver on behalf of modem is
never released and this prolongs the charge time. Move the
proxy vote to IPA3_POST_INIT before rmnet_ipa driver init
completes.
Change-Id: I271c8e6916d0c3068f720ae81b67f0fc5c198b6f
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
This can clearly show the firmware mode sent through QMI message
in the logs to help debugging.
Signed-off-by: Yue Ma <yuem@codeaurora.org>
CRs-fixed: 2059087
Change-Id: I0b11808f00229ed557141226bc2510673a7a1ede
An SDP may get detected as a FLOAT charger by PMIC APSD.
To handle this case do the following steps when a FLOAT
charger is detected -
1. Limit the ICL to 100mA and start USB enumeration
2. If enumeration succeeds, USB notifies a valid
ICL and the charger updates ICL and charger-type to SDP.
3. If enumeration fails, USB notifies -ETIMEDOUT and
charger applies ICL based on the Rp value.
CRs-Fixed: 2081457
Change-Id: I2747a42ed9f9531e83c53d781a8ae9baa9aa74d0
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Polarity should be updated based on HDMI resolution
for HDMI display. However, DSI interface does not need
to update polarity.
CRs-Fixed: 2046790
Change-Id: I4a30fcd7ebec70224accd2178c14bd37d2059f4e
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
SDA660 HDK platform has DP hardware blocks, so enable it in the
device tree.
CRs-Fixed: 2064346
Change-Id: Ieb524e37ed2f4cdd5776759b00ec182378ff6ff5
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
Thermal notifier callback is not allowing CPU
to come online. Rate limit logs to avoid watchdog
non-secure bite as it is a valid rejection due to
high temperature of SOC.
Change-Id: If3f8df7370e6ffd18b50e7451431d6a26023359d
Signed-off-by: Prateek Sood <prsood@codeaurora.org>
Make use of mutex lock to access IOCTL so that two threads
can avoid race condition.
Change-Id: I00db78a42c86eef8a157b5b3547e4ca0006b0853
Signed-off-by: annamraj <annamraj@codeaurora.org>
The rx ring buffers are added to a hash table if firmare
support full rx reorder. If the full rx reorder support
flag is not set before allocating the rx ring buffers,
none of the buffers are added to the hash table. When we
unload the module, this hash table is checked for freeing
the allocated rx ring buffers. Since none of the rx ring buffers
were added to the hash table, this memory is leaked.
Set the rx full reorder support flag before we allocate
the rx ring buffer to avoid the memory leak.
CRs-Fixed: 2081334
Change-Id: I6b7cbe05b914cf9aedd8e1ad54ccc4738f8b01e8
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
