Sometimes the HDMI is treated as non-pluggable display in auto
use cases. Add support to configure it through dtsi file, and
also provide timing parameters for the customized modes through
dtsi.
Change-Id: I2326b6c43cb7e6361be1f14d25f0e2e493c94177
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Include SDE DTSI for MSM8998 chipset. This
ensures that boards and targets using SDE driver
will use the new DTSI.
Change-Id: I9dfe8c48efbee5cb4f85fe684a06a2023abfda53
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
APQ8098 mediabox shall use the new SDE driver.
Disable the mdss_mdp device node on APQ8098 mediabox to avoid
duplicate probes.
Also make HDMI as the primary display for APQ8098 mediabox.
Change-Id: I9bea09473fccf2bf3048f0e0428b94bb16be3eda
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Rename mdss_mdp to sde_kms in the device tree to reflect the
new display DRM driver terminology and add support for HDMI TX
device node
Change-Id: Ide5dc6a5939945a3e993eca650c66a56f3955140
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Updating min frequency for memlat voting from 633MHz to
902MHz to avoid intermediate DDR frequency switching on
SDM660 target.
Change-Id: Ic68cbd15757bdc5ee1dbaef1d850a699c614837c
Signed-off-by: Nikhil Kumar Kansal <nkansal@codeaurora.org>
Add MDSS reg bus scale properties for sdm660 and sdm630.
These votes are required for faster reg access especially
in cases like histogram/gamut where we read large number of
registers.
Change-Id: Ia7aac81216b4138b583b37a938643eb950b5dcfc
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
In existing implementation elf region was being clearead before memory
access to firmware region assigned to HLOS. So to avoid it using
separate function which will be called only when HLOS is the owner.
Change-Id: I8bb22e4dbe3e1f898678d0c0f6e60268b88fc150
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Update the fuse corners supported for APC0/1 CPR instances of sdm630
as per the new fusing scheme.
Update speed-bin 2 frequency for TURBO_L1 to match the clock node
mapping.
Update the ceiling voltage limits for interpolated voltage corners
to that of their next fused voltage corner.
CRs-Fixed: 2008764
Change-Id: Iff104afa9750ba4be131cf142fc9eec01910678c
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add INT3_MI2S interface support for source tracking as INT3_MI2S_TX
is used for capture in the internal codec for SDM660.
CRs-fixed: 2007623
Change-Id: If0c72ad0942fc56b2778b831de019052c8fe31c0
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Timeout errors can occur because of execution error in device during
execution of last command. For errors encountered while executing
commands in card, like cmd46 or 47, the card will stop execution and
wait for the next command from controller to return error information.
If controller sends no command, then a timeout error will occur. To
retrieve the error information in card, send status command must be
sent. In case a non-timeout error like RED error is detected, there
is no need to send CMD13 to card as the error information is already
present in the Resp Arg register.
Change-Id: I6ac0d3db834a3d5a6c67ee08d6232240c35714ff
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Update the number of fuse corners used for APC0 and APC1 CPR
instances of sdm630 as per the new fusing scheme.
CRs-Fixed: 2008764
Change-Id: Icee251c350c102c698c2f60f3189e5aecf2dc7b1
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
When exiting low power modes (M3) do not reset
the DB Mode state if DB mode preserve flag is
set for channel.
CRs-Fixed: 1022868
Change-Id: I6557d28afe9d0ac11b76c683ffba76d7d6ffd377
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
In order to avoid being out of sync between MHI client
and MHI host, host shall not reset the doorbell modes for
hardware channels during MHI_M3 state transition abort.
CRs-Fixed: 1023725
Change-Id: I6c742fc968fd57d71a86039bf1f3f65b1362bc90
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
To avoid any race conditions between MHI_M2 state
transition and MHI_M3 state transition lock the
entire MHI_M3 transition using xfer_lock.
CRs-Fixed: 972390
Change-Id: I7c2e1b7b3966dc5fb8bf2f91bce734bbc58c6fd7
Signed-off-by: Tony Truong <truong@codeaurora.org>
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
There are instances when MHI channel context read
pointer can be accessed simultaneously by different
CPU cores. To make sure read pointer updates visible
to all cores, add a memory barrier after completion
of MHI ring operation.
CRs-Fixed: 966338
Change-Id: Ifc8c4cd7595fed9049009c42420a665fb170079f
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Currently all connectors list SDE as their parent interrupt
controller.
With commit <f5dd86c92d63df7a2790149d1cb9588c004695b0>
(<drm/msm/sde: reorganize top level interrupt handling code>),
the SDE IRQ domains get added after DRM init functions of the
connectors. This is incorrect as the irq request calls of the
connectors shall fail if the domain of the parent is not added yet.
Fix this by re-ordering the sde_kms_int() function to reflect the
correct order and remove the IRQ domain addition from irq_preinstall
calls as that will be very late for the connectors.
Change-Id: Ie1364840e2f018361e54470516d48c3facf59272
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add initial HDMI display driver support for SDE.
Support for configuring the HDMI TX controller
to specific resolutions. Add support for HDMI specific
ISR, uevent handling, basic debugfs support.
Add support for HDMI DRM specific calls for SDE driver.
Change-Id: I0cf7f4067e1a9b378632713b896798971971e5b9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
The ADSP edge has strict timing requirements for audio usecases.
Enable GLINK QOS feature for ADSP to ensure timely tx transactions.
CRs-Fixed: 2009756
Change-Id: I8abc6a9c7b89d04f42ac1600251b3813b1677c38
Signed-off-by: Chris Lew <clew@codeaurora.org>
Add routing controls to connect analog and digital codecs for both
RX and TX paths.
Change-Id: I9d9c9b07c11ad0c36c4e5726b3466f02f2f9ef6c
Signed-off-by: Divya Ojha <dojha@codeaurora.org>
Correct widget type for proper power up sequence. Pops are heard
on headset with incorrect sequence.
CRs-Fixed: 2001499
Change-Id: I98703738434f99e5c8778ccd4432c66b380d78a5
Signed-off-by: Divya Ojha <dojha@codeaurora.org>
Bring in refreshed register definitions from the rnndb database.
Change-Id: Ic0dedbaddd22f6ac0b8cfb6184073968569de22d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add device tree file for analog audio over USBC support
for MTP platform of SDM630.
Change-Id: I71559108a94890cdb1cbdf4ac76eab92a56ff953
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Add device tree file for analog audio over USBC support
for MTP platform of SDM660.
Change-Id: I676b1a361d1c9f89707703f50afe9b3f614beaaa
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
