Update the MISC settings register according the color
depth and format. Update the MVID and NVID registers
using the M and N values used to configuring
the DP pixel clock.
Change-Id: I67e08d3491fbb7c0960c463cc8f979238b89d818
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Since usleep_range provides better accuracy in
comparison to msleep. This helps in reducing the
latency of host bus resume.
Change-Id: Id22104b9e5b63153731df9eb55759de9a86128c6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
A540v1 and v2 both need to enable the LMLOADKILL quirk for the
GPU.
CRs-Fixed: 1036444
Change-Id: I84243578a1ef2f9948f0c9a8c1c00dc6a31eb579
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL
and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers.
This is done to avoid a VPC corner case with local memory(LM)
which leads to corrupt internal state on A540 and its derivatives.
CRs-Fixed: 1036444
Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Embedded tputs depend on WAN RX desc size, but, every target
has its own limitations of memory and embedded tputs goals.
So, add parameter to configure WAN RX desc size through device tree.
Change-Id: I28c550058dd990c9c8cd368a2677097c7f057ccd
CRs-Fixed: 1081543
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Based on the hardware documentation, update the IMA error
handling and clear sequence. In addition, check for DMA errors
and clear it before SRAM transactions begin. Also, check for IMA
hardware status to run the IMA clear sequence during ima_init and
not just based on IMA exception status alone. This is to help
with FG SRAM access to resume again properly in case of an error
encountered.
Change-Id: I583fa51599a1cbbd029cb45c075429730d2e071b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
When running concurrent video session, there are some possibilities
that CPU may take more than a second to schedule hfi work handler.
In those cases, one of the threads which is waiting for the response
is timing-out.
Increase hw response timeout and power collapse timeout will give
more time for hfi work handler to be scheduled and process the response
messages.
CRs-Fixed: 1086284
Change-Id: I768ef6c941c791af5a45d846fa81d810b831efa5
Signed-off-by: Karthikeyan Periasamy <kperiasa@codeaurora.org>
Current display driver prints warnings and errors within
the mdss spinlock. This causes in random cases to hold the
spinlock for long time when multiple errors are printed;
Fix this by moving the print of warning and error messages
outside of the spinlock.
Change-Id: I09359b528b4742f72a76690930f3d0ed90bb2caa
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
