When running concurrent video session, there are some possibilities
that CPU may take more than a second to schedule hfi work handler.
In those cases, one of the threads which is waiting for the response
is timing-out.
Increase hw response timeout and power collapse timeout will give
more time for hfi work handler to be scheduled and process the response
messages.
CRs-Fixed: 1086284
Change-Id: I768ef6c941c791af5a45d846fa81d810b831efa5
Signed-off-by: Karthikeyan Periasamy <kperiasa@codeaurora.org>
Video kernel modules as LKM make the T32 debugging difficult.
So, We revert the change and make video drivers as part of boot image.
CRs-Fixed: 1086328
Change-Id: Icd8aa9f935eb0096d1e13934ea556c74d7341093
Signed-off-by: Karthikeyan Periasamy <kperiasa@codeaurora.org>
Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.
Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
On ARM systems the cache topology cannot be probed at runtime, in
particular, it is impossible to probe which CPUs share a given cache
level. Power management software requires this knowledge to implement
optimized power down sequences, hence this patch adds a document that
defines the DT cache bindings for ARM systems. The bindings are compliant
with ePAPR (PowerPC bindings), even though most of the cache nodes
properties requirements are overriden, because caches geometry for
architected caches is probeable on ARM systems. This patch also adds
properties that are specific to ARM architected caches to the existing ones
defined in the ePAPR v1.1, as bindings extensions.
Change-Id: I37ca3aae0471fcd60499615df77093d5b5451bf8
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
If "core" memory resource is not specified, the driver could end up
dereferencing a null pointer.
Fix this by returning -EINVAL when core resource is missing.
Change-Id: Id08f7b2e109b6b2963b19dfe07f07cbfb424202b
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Rec2020 CSC type will be set by hwcomposer when incoming YUV data
is of the same type.
CRs-Fixed: 1081779
Change-Id: I321bd79d04e135030764dcdf83a58fee3c4e72c8
Signed-off-by: Benet Clark <benetc@codeaurora.org>
In case RG10 workaround is in use, USB disconnect sequence
needs to be delayed until uC image is loaded in order to
allow to suspend and unsuspend pipes successfully.
Change-Id: I0ba41c9564c12b0b2c419222b54fa0e05be93b75
CRs-Fixed: 1083675
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
