Currently strobe control is cleared even when HW strobe control is not
explicitly enabled. Fix it.
CRs-Fixed: 1077179
Change-Id: I5bc6a5a46311206818d70567e31fd84adc0128be
Signed-off-by: ansharma <ansharma@codeaurora.org>
Initial support for all BLSP SPIs with default configuration
and disabled state such that clients can overwrite and enable
respective SPI instance as per need.
Change-Id: Ia60fc3ecb5c2aba19effe1c8242f2d89fdef3ebd
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Controller driver explicitly puts the controller in low power mode
when cable disconnected. However, due to config-fs and ADB design
which unbinds composition on every cable disconnect results in
detaching/stopping gadget driver on every cable disconnect. Gadget
stop will explicitly brings the controller out of low power mode to
disable events and ep0 which is not necessary as controller is
already in low power mode. These operations are not required for
composition switch as well because gadget pull-up call back will
take care of that. Hence, Remove disabling events and ep0 from stop
gadget callback.
Change-Id: If2b3e241076a4e0eeb87eeb4361398313fca6962
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Initialize mbhc pointer before it gets accessed from
a different thread.
Change-Id: Ie1a5038458b0b93dfec3e5bfc350686eb1f8eb1b
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Add support for printing the voltage voting info to the
clock_state ftrace events.
CRs-Fixed: 1082843
Change-Id: I6ab3992958a659995b7d5020287fd6e47e28f2a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.
Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
On ARM systems the cache topology cannot be probed at runtime, in
particular, it is impossible to probe which CPUs share a given cache
level. Power management software requires this knowledge to implement
optimized power down sequences, hence this patch adds a document that
defines the DT cache bindings for ARM systems. The bindings are compliant
with ePAPR (PowerPC bindings), even though most of the cache nodes
properties requirements are overriden, because caches geometry for
architected caches is probeable on ARM systems. This patch also adds
properties that are specific to ARM architected caches to the existing ones
defined in the ePAPR v1.1, as bindings extensions.
Change-Id: I37ca3aae0471fcd60499615df77093d5b5451bf8
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
If "core" memory resource is not specified, the driver could end up
dereferencing a null pointer.
Fix this by returning -EINVAL when core resource is missing.
Change-Id: Id08f7b2e109b6b2963b19dfe07f07cbfb424202b
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Rec2020 CSC type will be set by hwcomposer when incoming YUV data
is of the same type.
CRs-Fixed: 1081779
Change-Id: I321bd79d04e135030764dcdf83a58fee3c4e72c8
Signed-off-by: Benet Clark <benetc@codeaurora.org>
