Rather than using debugfs, switch to tracefs which trace
moved to in kernel 4.4.
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: I52ef7d45cabb20cc61fbd2fb3ef5016b041bc56c
PCIe PHY varies between each chipset. Thus, the PHY init sequence on
each of these chipsets are also different. Therefore, add the support
to read PCIe PHY init sequence from devicetree.
Change-Id: I21c2ce2b7d3bf1541a5d3580db4bc40497701095
Signed-off-by: Tony Truong <truong@codeaurora.org>
Although rotator driver checks for hardware version, and rejects
unsupported version. But it does not return error code to indicate
error condition, and causes driver crash.
This fix adds error code to unsupported version, so upper layer can
properly handling the condition.
CRs-Fixed: 1015335
Change-Id: If83199b5990a3623b1018058d2164862352902b7
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Disable the OSM vred FSM until core-count adjustments are enabled
for the CPRh VDD_APC0 and VDD_APC1 devices.
Change-Id: I467f49edbc65449f29f761c6b873ca702d24fa72
CRs-Fixed: 1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add additional required clocks to mdss device tree to enable
mmss smmu and ahb access for rotator.
CRs-Fixed: 1008505
Change-Id: I5bfc16e3d6ac3c6052b8dca55b42b57480ec650e
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Fixes 2 problems related to multi-kernel tree support:
1. Copying of modules to /system/lib/modules is broken when building
in a multi-kernel tree. This is because INSTALL_MOD_PATH is not
set correctly. When building a multi-kernel tree, the output
directory is one additional directory deep, so modules end up
under <out>/obj/system/lib/modules instead of
<out>/system/lib/modules. Fix this by using BUILD_ROOT_LOC
which is set appropriately for multi-kernel and standard trees.
2. When running "make kernelconfig" on a multi-kernel tree,
the generated defconfig is copied to the wrong location,
since it uses the old-style location under kernel, instead
of kernel/<kernel name>.
Change-Id: I90563104a5b6219472eaeae1964fc34b52586536
CRs-Fixed: 1014872
Signed-off-by: Lior David <liord@codeaurora.org>
Some MSMCOBALT parts with CPR revision 0 are unable to operate at
low voltage. Therefore, raise the CPR floor voltage to be equal
to the Nominal ceiling voltage for all corners. Also increase
the ceiling voltages for corners accordingly to ensure that the
ceiling >= floor voltage requirement is met.
Change-Id: I346a909984519c2522503f842d449c6f3217b746
CRs-Fixed: 1014407
Signed-off-by: David Collins <collinsd@codeaurora.org>
Enable ssphy and update the qmp phy initialization sequence
to enumerate in super speed mode. By default Lane A is
selected for super speed mode.
Change-Id: Ibd5fdd0a1f48ecd8a828d187ac86513e3f48ae6f
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Add mmss_mnoc_ahb clock to mdss device tree as this clock needs to be
turned on before turning on ahb_clk.
CRs-Fixed: 1008505
Change-Id: I43ccff9774d098d551c4ba25ad5678fee13aca1f
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Add new USB rx and tx afe ports and routing to different
fe dais to enable USB audio via ADSP.
Change-Id: I4f82ba27becee1f3b62c410be0d00876961f9b18
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
The only dependency for irq time accounting is a sufficiently high
resolution timer. Plenty of arm64 platforms will have this, so enable
this feature.
CRs-Fixed: 1013947
Change-Id: Id675a541a6813a14ae0b7e1bb66670bf7467a97f
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
[satyap@codeaurora.org: trivial merge conflict resolution.]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Enable CPUSS dump driver to dump cpu subsystem during crash.
CRs-Fixed: 1011333
Change-Id: Id4a8bca3eb77db4f998c790f1927fe373684048a
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
This snapshot is taken as of msm-3.18 commit dacccc6.
CRs-Fixed: 1011333
Change-Id: I4ed06b5602220ed4e30bd37a0633ccb3454f7d43
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Use correct index value while accessing DCI channel status.
Change-Id: I97456326a40c6d24c208307a9e8e6a55fc5b9d59
Signed-off-by: Sreelakshmi Gownipalli <sgownipa@codeaurora.org>
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The pcie_aux_clk_src needs to run at XO frequency instead
of at 1MHz. Update the clock driver to support that.
CRs-Fixed: 1013278
Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the base address of GPIOs to the correct value.
CRs-Fixed: 1014950
Change-Id: Id232492bd458dac04e89a94ed5a85092223ebff6
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
This change separates the control and config register offset nodes
for ping pong blocks. Its not necessary every ping pong
blocks to have both control and config registers.
Change-Id: Ide998ad71abccb35d899f9e1f6093949acb95b09
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
With LMH DCVSh hardware, the current check will use cpufreq to
limit both scaling min and max frequency. But cpufreq should be
used only for scaling min frequency.
Update the check to use cpufreq only to limit scaling min frequency.
Change-Id: I38de1699a7cdd5bc3fecef80dd34c4d22d2fd200
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
With LMH DCVSh hardware, thermal driver can directly vote in the
hardware to limit the scaling max frequency. Voting to the cpufreq
driver along side the hardware, will introduce software delay when
removing the mitigation.
So avoid voting the scaling max frequency to the cpufreq when LMH DCVSh
is available.
Change-Id: I8a5f913ae41263b06af99b0ee802b4fa68312f33
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Enable bcl peripheral driver. The driver will interact
with the bcl peripheral to get the battery current, battery
voltage and set and receive thresholds for the same.
CRs-Fixed: 1010115
Change-Id: I7168c754e939ef9da001bcac52a5b802dea40b41
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Add slimbus_6_rx back-end dai-link for msmcobalt to enable
independent backend for different devices during audio playback.
Change-Id: If22cadbcfac92f8243a3b6d3201935a839cd701a
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Add device tree entries for USB audio rx and tx to
support USB audio via ADSP on msmcobalt platform.
Change-Id: I345aa2369d18e2137ce79676049bb59d715d1ee0
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
GSO segmented packets are getting linearized
before being sent to rmnet_ipa interface since SG
feature is not enabled.
Add NETIF_F_SG to IPA's HW features so that
ethtool can be used to enable it.
Change-Id: I7b321c796935febb3fa3e9ae520fd65e00da507c
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Camera sensor probe happens in camera daemon, because
of delayed start of camera daemon, timeout happens and
camera server is notified with 0 cameras, this is
temporary solution.
CRs-Fixed: 1014373
Change-Id: I957b9744f6f627a74f805933012429c41b910e92
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Commit a240321fd6 ("ARM: dts: msm: define
primary display interface for msmcobalt CDP") used an incorrect binding
to specify the panel mode selection gpio state for the nt35597 WQXGA
dual dsi panel. Fix this to ensure that the panel mode gpio state is set
correctly.
Change-Id: I895642c231d980633801d094c8f329d209370c88
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Configure the bcl peripheral driver with the details about the
register address, interrupt and interrupt clear polling delay for
PMIcobalt.
CRs-Fixed: 1010115
Change-Id: I521ee6c715525bd401630ec7948e5746682de6da
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Correct the pinctrl nodes for actuator, change the CCI
source for auxiliary camera node, add eeprom1 node for
auxiliary sensor.
CRs-Fixed: 1014373
Change-Id: Icd9f1478c797fbdbd76d96c3069e5baa2c30ff61
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Add support for the new version of bcl peripheral introduced
in PMIcobalt.
The new support includes,
1. support the new address space
2. set the new Ibat too high threshold
3. set the new vbat low comparator threshold
4. set the new vbat too low comparator threshold
5. enable the LMH DCVSh monitor algorithm, when the
thresholds are configured.
CRs-Fixed: 1010115
Change-Id: I6dad908bbc673ff1b7f7d3d05fecdfc8f48b5815
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
This snapshot is taken as of msm-3.18 commit
978d23c.
Accommodate the changes in the input arguments for
power_supply_register() API and use
power_supply_get_property() API to get the SoC information
from BMS.
CRs-Fixed: 1010115
Change-Id: I1af565ffd3b61e424aca1cbd5ec6cbef8d89f1fa
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Add mnoc ahb fab used by clients to request for different
speeds on configuration paths.
CRs-Fixed: 1013346
Change-Id: Ic5f3598644a6d93796b8613117e42ff692168c3c
Signed-off-by: David Dai <daidavid1@codeaurora.org>
To prevent a 0 vote on to bimc_clk from late clock init,
there must be a non zero vote on bimc_clk's child as opposed
to itself, vote on the child clock node as opposed to the parent.
CRs-Fixed: 1013348
Change-Id: Id3a9fa3238ce0f04737a7b98aa897ec83ecdc8e2
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Add support to access system's memory.
CRs-Fixed: 1013668
Change-Id: I7cafb74373efbc611bc894bdf3b351aae7e03da5
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Debugfs directory creation failure are not critical error.
However, the failure messages might be misleading and might
be interpreted as geniune failure in ASoC functionality.
Mark the failure messages as debug level.
Change-Id: Id61c81753d493b6508cbe87c59077adda4675ada
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Program the PLL test control register for the power
cluster clock in agreement with hardware guidelines.
Change-Id: I102fd544ea0571d31d2ef9232195d4adbddda6d7
CRs-Fixed: 1009203
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Configure the mode selection GPIO as direction output in order to
correctly configure the panel operating mode.
Change-Id: Ic79850674c42f3c59512467dbb608942b98cf74a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Initialize the op_mode register and program the direction_enable
field in this register correctly
CRs-Fixed: 1008505
Change-Id: I2dbcb8eb1ef5c6e0ebcbfb9f298a14344fbe7ce3
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Enable VADC_HC and BTM peripheral driver on PMcobalt
to support reading and setting thresholds on ADC
channel such as voltage phone power(vph_pwr) and
thermistors.
Change-Id: I783d87714145f58fefc9e1e6a09d1ecfab56744b
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
The current method of cat-ing register file dumps the entire
address space. One can use dd command to dump a subrange within
the address space. However one needs to know the string length
of each line which is derived from max address, the character
length of each register entry and the format.
Provide simple means to dump a range by allowing user to specify
the start address and the count of registers. When the data is read
convert the dump address to a starting position in the file. Similarly
if the file offset goes beyond the dump range return 0 to indicate
that the data is already dumped.
Also provide means to write to a register address.
CRs-Fixed: 1001770
Change-Id: I3466ce89007d127151f6760328edad116d679db8
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Support retention by checking interrupt status rather than logical
address register. During retention, interrupt status is zero'ed but
logical address may be retained to avoid report-present generation.
Change-Id: I9e7f24c5f4eb722643bf3fac2d5c898ad107dd24
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Update v4l2_event32 structure with updated elements
from v4l2_event structure. Also copy and update
reserved and other fields during 32 bit ioctl handling.
CRs-Fixed: 1013345
Change-Id: I3038a2c0c7f2b7f13c412dc04890744d8dbe37ee
Signed-off-by: Arun Menon <avmenon@codeaurora.org>
Enable Coresight drivers for msmcoblt. These devices can be used to
configure and enable trace functionality on msmcobalt.
Change-Id: Ib4b50d7df15114d417898c36b229441766bd5b42
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add the property to determine GPU bitness which
is used by the clients via KGSL ioctl.
Certain clients of KGSL such as Open-CL driver
need to know explicitly about the GPU mode.
Change-Id: I77523d7816edb9776014aaf3aa85321af0d20aaf
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
The host AHB aperture for reading the HSLQ/SP/TP and shader memory
blocks might be blocked on A5XX targets so use the CP crash dump
utility to read them instead. Downside if the crashdumper goes boom
we'll have to skip those registers in the fallback.
Change-Id: Ic0dedbad3c7b485c696198bdfcb78d45e929ec22
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
A505 GPU is having two different frequency plans, for
loading a specific frequency plan add speed bin read
information capability to A505.
Change-Id: I259020d7e4613d043e213ab2cb41e80ceb11f46a
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Do not allocate memory for IB descriptors for commands
of types profiling buffers, sync and markers.
This fixes the memory leak due to allocation of
memory for such commands and these were never freed.
CRs-Fixed: 996651
Change-Id: Ib168d60ad89e0fd55cd1f10b773b7cdaa7400ace
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
This change includes the below:
- Add 1M and 8k pools and structure the allocator to use all pools
from the largest page to the smallest
- Reserve a set number of pages for each of these pools at init time
- When allocating, use the reserved pools and then fall back to
allocating from system memory using only 8k and 4k pages
- Remove maximums on the pool sizes
- Zero the memory when we create the pool initially and add pages
back to the pool on free
CRs-Fixed: 995735
Change-Id: I9440bad62d3e13b434902f167c9d23467b1c4235
Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
When IPA clock is enabled, suspend bit is cleared
and if pipe is non-empty EOT is posted internally.
At the same time, there is a possibility that SPS
driver posts EOT. This can result into incorrect
state of polling state and switch to intr mode is
tried repeatedly. Make a change to check if we are
in intr mode already in addition to the polling state.
Change-Id: I1af08605f7d2d234b0e5a4e3c8928db6cff5c7b4
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
There is a new Qualcomm Technology Inc. Plug-n-play(QPNP) PMIC chip,
which introduces brand new flash LED hardware. The new hardware
comes with up to 3 LEDs support, different register mapping layout,
and different torch enablement requirement. Therefore, a new driver
is introduced to cover this need.
Change-Id: Ic878f1a946955edff3a9228e7fe54b7a525e37b1
Signed-off-by: Chun Zhang <chunz@codeaurora.org>
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
