Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.
CRs-Fixed: 1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
MHI transaction status stores the OVERFLOW status
received from device. MHI clients uses this
status to determine overflow buffers, do
not clear the status.
CRs-Fixed: 1042516
Change-Id: Iaaff06c1c39775d6a33ca17851f1e1579b2a2ecb
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
When checking for available spaces, check available spaces on
both bounce buffer ring and transfer ring and return min.
Change-Id: I9208b46c32821de3f5d9e3d828087d7bc29b9546
CRs-Fixed: 1055681
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add missing state MHI_STATE_RESERVE to MHI states
look up table.
CRs-Fixed: 1049595
Change-Id: I9a6bd2750f81f6cabc1e7b5aff488b4a01f7897d
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Get the iova for a buffer object from the context
specific address space instead of always defaulting
to the global address space.
Change-Id: Id38c2ca2d6bad334beab53d8bcf8eb5cf5b1bb99
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Return the current status of the fence (0 for retired, -EBUSY for
active) if an absolute timeout of 0 is passed to MSM_IOCTL_WAIT_FENCE.
This allows the user space to check the status of the fence without
an awkward timeout or an inadvertent kernel message.
Change-Id: Ic0dedbad66adfabed24aeb6692abb2765ee37f24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The PFP/ME and GPMU memory needs to be GPU accessible but it
does not need to be written by the GPU. Mark them as read-only
to avoid corruption.
Change-Id: Ic0dedbadc848f0a6693a4e57567077bbab38e9a5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There isn't any need to be in secure mode when executing the GPMU
initalization so swap out to eliminate it as a variable when
GPMU init goes broken.
Change-Id: Ic0dedbad07b8cde80e257f71999002e9cbc47c24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enable pm_runtime for the GPU to keep power collapse from hitting
us while we expect the GPU to be powered.
Change-Id: Ic0dedbad693f1d01776a87bc7a145a65510ac3fb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
If we do not enable the iommu clocks at attach time they might
be shut off automatically by other devices power collapsing which
would affect our ability to switch the pagetable dynamically.
There is little power downside to just leaving them on all the time,
or at least as long as the main device is attached (in other words,
all the time).
Change-Id: Ic0dedbad8f6d2ee2a2cb9516e062af2421d91052
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The overrun check for the size of submitted commands is off by one.
It should allow the offset plus the size to be equal to the
size of the memory object when the command stream is very tightly
constructed.
Change-Id: Ic0dedbadec41fb8be84d7522b4dc923dbd537ce5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
When a fault happens on the Adreno GPU we want to collect
a considerable amount of information to diagnose the problem
including registers, caches, and GPU memory structures (ringbuffers,
etc).
The snapshot collects all of this information following a GPU fault
and encodes it into a binary file format that can be pulled from
debugfs or extracted from a memory dump.
This may seem a duplication of other debug methods (the ->show
functions for example) and while that is true for small numbers
of registers the snapshot goes much further - it collects hundreds
(thousands) of registers in addition to memory and other structures
that would be impractical to dump as ascii. The binary format allows
for the snapshot to be easily shared and post-processed in different
ways to extract patterns.
Add the basic snapshot infrastructure and enable ringbuffer, register
and shader bank collection for A5XX targets.
Change-Id: Ic0dedbadcf0513096d05870f522ac73da74ceb31
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Change-Id: Ic0dedbade1264785b3436099e638a5678a62818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Update the list of the A5XX register ranges that can be read on a
hang. The new list adds some registers that were previously missed,
and omits registers that are write only.
Change-Id: Ic0dedbadaf6969892c0563d9cfd8fa2869008417
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Instead of using a fixed list of clock names, use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Change-Id: Ic0dedbad629743ff078177c301ffda3dbce88d3c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses.
Change-Id: Ic0dedbad3769801b62152d81b37f2f43f962d308
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more reliably mapped into the
instance's GPU VM space without conflict.
To support this create a new dynamic domain (pagetable) for each open
DRM file and map buffer objects for each instance into that pagetable.
Use the GPU to switch to the pagetable for the instance while doing a
submit.
Change-Id: Ic0dedbad22d157d514ed1628b83e8cded5490dec
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighborhood IOMMU driver.
Change-Id: Ic0dedbaded3a9e57a7fbb8e745c44c183f6b4655
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Change-Id: Ic0dedbad3761b0f72ad6b1789f69458896214239
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Allow a domain to opt into allocating and maintaining a TTBR1
pagetable. The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region.
By example, given a TTBR0/TTBR1 virtual address range of 36
bits the memory map will look like this:
TTBR0 [0x000000000:0x7FFFFFFFF]
TTBR1 [0x800000000:0xFFFFFFFFF]
The map/unmap operations will automatically use the appropriate
pagetable for the given iova.
Change-Id: Ic0dedbad2b2c58cd9c47ce31356472e0463d4228
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing by default but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
possibly using addresses above 4G for those targets that support them.
Change-Id: Ic0dedbad7e527c4b1fe87878e943619c5e0ad869
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Change-Id: Ic0dedbad6c62d6859c90764245437c222d61f00d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Change-Id: Ic0dedbad428360d23768d52b585021237c6bc3d3
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Remove the IOMMU_WRITE bit from buffer objects that are
marked MSM_BO_GPU_READONLY. Add a new flag (MSM_BO_PRIVILEGED)
to pass through IOMMU_PRIV for those IOMMU targets that support
it.
Change-Id: Ic0dedbad8d9d3f461a47ea093fad3fdd90f46535
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Change-Id: Ic0dedbadca31e835f014037ea3f9741048df3b98
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while it is being written. This isn't a huge deal
with a single ring (though technically the hangcheck could assume
the system is prematurely busy when it isn't) but it will be rather
important for preemption where the decision to preempt is based
on a non-empty ringbuffer. Without a shadow an aggressive preemption
scheme could assume that the ringbuffer is non empty and switch to it
before the CPU is done writing the command and boom.
Even though preemption won't be supported for all targets because of
the way the code is organized it is simpler to make this generic for
all targets. The extra load for non-preemption targets should be
minimal.
Change-Id: Ic0dedbad83247c3e77de6f4f24bbb97db10e5edd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
