Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Matt reported that we have a NULL pointer dereference
in ppp_pernet() from ppp_connect_channel(),
i.e. pch->chan_net is NULL.
This is due to that a parallel ppp_unregister_channel()
could happen while we are in ppp_connect_channel(), during
which pch->chan_net set to NULL. Since we need a reference
to net per channel, it makes sense to sync the refcnt
with the life time of the channel, therefore we should
release this reference when we destroy it.
Fixes: 1f461dcdd296 ("ppp: take reference on channels netns")
Reported-by: Matt Bennett <Matt.Bennett@alliedtelesis.co.nz>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linux-ppp@vger.kernel.org
Cc: Guillaume Nault <g.nault@alphalink.fr>
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Git-repo:https://source.codeaurora.org/quic/la/kernel/msm-4.4
Git-commit: 205e1e255c479f3fd77446415706463b282f94e4
Change-Id: Ic7ce3be365ebdc1505ed8ce68df981c855638a3c
Signed-off-by: Srinivasa Rao Kuppala <srkupp@codeaurora.org>
When the GPU hardware init function fails (like say, ME_INIT timed
out) return error instead of blindly continuing on. This gives us
a small chance of saving the system before it goes boom.
Change-Id: Ic0dedbad142efbc9bd93e8531b40c391ec15f557
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Make sure to detach the MMU device before destroying the address
space.
Change-Id: Ic0dedbadff27fed017840a61ec5e0d55ce0c71e6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
SDE and the GPU have different requirements for the SMMU backends - the
SDE generates its own iova addresses and needs special support for DMA
buffers and the GPU does its own IOMMU operations. Add a shim layer to
aspace to break out the address generation and call the appropriate
SMMU functions. There is probably consolidation that can be done, but for
now this is the best way to deal with the two use cases.
Change-Id: Ic0dedbadc6dc03504ef7dffded18ba09fb3ef291
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We can have various combinations of 64b and 32b address space, ie. 64b
CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So
best to decouple the device iova's from mmap offset.
Change-Id: Ic0dedbad2b36b535df3e8fb2ddddc20add592cea
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 22877bcbdacd50d076f9b2f829e6a3753aa9821f
Git-repo: https://github.com/freedreno/kernel-msm.git
[jcrouse@codeaurora.org: Fix merge conflicts, remove mdp5 due to large
infrastructure changes, compile fixes]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Currently, IPA driver asserts if IPA FW loading
fails. Some environments do not have IPA FW
integrated and we should not crash at these cases.
CRs-fixed: 2005599
Change-Id: I78b9f2cadb8c35ab455f4514c7efc9cee4cf4542
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
Update cpufreq table for sdm630 as per new cpu clock plan.
CRs-Fixed: 2008773
Change-Id: Ibaa5d3c2d1dbafd14b5e9bee382cd3980f89aa51
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add device tree files for headset jacktype NO, for CDP
and RCM platforms of SDM630.
Change-Id: I297e6467ed47c51950ae527077c3d20cf738e0b6
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
ICL change interrupt triggers whenever there is change in the
input ICL, in case of AICL restart(done as part of S/W base
pulsing) AICL starts from 500mA and ICL change gets triggered
for every 25mA ICL as part of AICL ramping.
ICL change handler generates a power_supply event on parallel
psys and thus causing parallel framework to re-split ICL for
every 25mA. Fix this by delaying power_supply event until AICL
settles.
Change-Id: I9270a99f536db4534e46764b2e053ff93b38cb54
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Hardware autonomous INOV does adapter's output voltage
manipulation only based on the input limited state of main
charger. This works well with MID-MID parallel configuration
but with USBIN-USBIN parallel configuration parallel charger's
input limited state also plays role for INOV manipulations.
Thus disable hardware based autonomous INOV and add support
for software based INOV for USBIN-USBIN configuration.
Note that if authentication is disabled, the hw assumes QC3.0 and
if the autonomous bit is enabled, it issues increment/decrement pulses.
This happens even when QC3.0 has not been actually authenticated.
Change-Id: I397acb558c9ba3b6fc7d7b974d64459f278697fd
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
