In async commit case, driver needs to always wait for input fence
before triggering the complete_commit path. Otherwise, there could
be tearing since GPU hasn't finished the composition rendering.
Change-Id: I73a54f5811fdcf8639618ce3cacf4cbaa00b406c
Signed-off-by: Felix Xiong <xayang@codeaurora.org>
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
The SPLIT related registers are only for DSI interfaces. Without
checking the interface type, they could be overwrote by
configurations through HDMI path.
CRs-Fixed: 1085586
Change-Id: I7ace9fd8dfe5ee99cb750b2723e8f22701039552
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
The h/v polarity should always be set from the panel configuration.
For HDMI display, it's from the EDID information. For DSI display,
it's from the panel settings in the dtsi.
CRs-Fixed: 1085021
Change-Id: I3776603d7055e69eb2c8e5003ab83bc0483ab7c8
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
The initial version of the patch save the command submit_time and
queue_time in seconds, but its desired by the users of this profiling
API to return the time in nanoseconds resolution.
Change-Id: I3a56e3ffd3ebe86f51a00a12b7c3e7c4b4c9a956
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
At this point, there is nothing left to fail. And submit already has a
fence assigned and is added to the submit_list. Any problems from here
on out are asynchronous (ie. hangcheck/recovery).
Change-Id: Ib6b6bf00099137972649c97cc6cd8c4fe25ce7c3
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 1193c3bcb581807d58dd7df90528ec744af387a9
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[smasetty@codeaurora.org: fixed merge conflict issues; made corresponding
changes to A5XX submit function.]
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
This patch contains fixes to prevent the CRTC's atomic check
from inadvertently adding extra plane states to the current
state object.
CRs-Fixed: 2037970
Change-Id: Ic0b09ab369f77c2412ba7c3e63fe5032ef9bcd74
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Simplify the clearing of the topology name by moving it directly
to the release resources call.
Change-Id: If1926372b276f01f64138691b805493d1894951a
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
SDE HDMI driver capabilities were capped
to 1080P due to lack of dual pipe support in userspace.
Relax this restriction as full userspace support to
allow dual pipe support is now available.
Change-Id: If8242ea3c65a901ceb3e1004ac40b29ab8554c4b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
HDMI connector should wait for audio codec status and notify
HPD status only in case that audio codec has been registered
successfully. Meanwhile move HPD notification to bridge enable
and disable instead of hotplug work. This ensures the correct
video and audio sequence.
Change-Id: I0dac915c8639bb881265a608016e9d37ec9a153c
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
For some optimizations coming on the userspace side, splitting larger
draw or gmem cmds into multiple cmdstream buffers, we need to support
much more than the previous small/arbitrary limit.
Change-Id: Ic0dedbad2f79156f4e6c9f70c8e27cd5fff9acdb
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 6b597ce2f7c7a0f8116d753902db9aba6bc05cb0
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[jcrouse@codeaurora.org: fix some merge conflicts]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Zero sized buffer objects tend to make various bits of the GEM
infrastructure complain:
WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 drm_mm_insert_node_generic+0x258/0x2f0
Zero sized buffers serve no appreciable value to the user so disallow
them at create time.
Change-Id: Ic0dedbada2a0250227d7ee8c45c35dc92a826c67
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Allow the user to allocate and use secured buffer objects. Secured
buffer objects are suitable for use as a write target while the GPU
is in secure mode. They work exactly like regular buffers except
Secure buffers cannot be mmap()ed.
Change-Id: Ic0dedbadd8135fd8472b38ddf61e2bc70983b12f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Check to see if an imported buffer is an Ion secure buffer and mark
it as such so that it can be used for secure rendering.
Change-Id: Ic0dedbadb414dcbb11d70785d61481a1b7bd4e19
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
A5XX targets support GPU rendering on secured surfaces by going
into a special secure mode to execute the commands. In secure mode
GPU rendering can only write to secure buffers that have been mapped
in an appropriately secured pagetable. In secure mode the GPU can read
both secure and unsecure buffers and the CP engine can only access
unsecured buffers (so commands do not need to be secure).
Secure buffers virtual addresses must fall into a specific range; this
is the clue to the GPU that it should use the secure pagetable
instead of the regular one. For A5XX targets that range will start
at 0xC0000000 and be 256MB in size. All secure buffers in all processes
share the same pagetable.
Add a secure address space for A5XX targets and automatically trigger
into secure mode if any buffer in the submission is marked as secure.
Change-Id: Ic0dedbad8f7168711d10928cd1894b98f908425f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The "_header" field of the macro was being incorrectly expanded to just
"header". This was only working because all the functions which used this
macro already had "header" defined in scope.
Change-Id: I19e77ae78cfff471ddffd428cb3fd055c6340737
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
This patch helps dump the full 64k per ring preemption
record to GPU snapshot which is collected during GPU
recovery step. We use the general object snapshot section
type to store these records and we only collect the preemption
records if preemption was going to kick in, which is when
the number of rings is greater than one.
Change-Id: I1872bc14c6b39c8c4963ce9c98e96b03cbfec907
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
When enabling animation/state splash in LK, drm/kms driver needs
to involve handoff code to support smooth transition. In display
probe it will do following items:
1. Check the status in LK for early splash.
2. Handle SMMU mapping issue to avoid SMMU fault problem.
3. Reserved memory, and bypass hardware reset to avoid glitch.
And after user's space is up, when first commit comes, it will call
sde_splash_clean_up to:
1. tell LK to stop splash and to exit.
2. set early_domain_map_attr to 1 to enable stage 1 translation in
iommu driver.
3. free the memory to system.
Change-Id: If425f044e2c40301eed57375a33a26ec1970abd5
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Driver customizations for sde clients should be disabled, or sde plane
behavior would be unexpected.
Change-Id: Ic42e4e692f6702667bb63b7fc9cf62bf705c446d
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
With the upcoming secure code the decision tree for configuration
(deciding where virtual addresses start/stop, etc) is going to get
a bit more complex. Head issues off at the pass by moving the
configuration into the GPU specific code. This does result in a
bit more code duplication but it is a lot cleaner.
Change-Id: Ic0dedbad57c11a4bba01825214d0a7853ab537ba
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add support for creating a secure domain in the GPU IOMMU. By default
the secure domain is bound to context bank name "gfx3d_secure".
Change-Id: Ic0dedbad19f69ec4175624dc80f2114bfda2e195
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
None of the existing iommu implementations use the names passed in
at attach time by the API. Save a bit of .data room by removing
the static string definitions and passing NULL to the attach function.
Change-Id: Ic0dedbada9561768b8d9716ea101619e6b549ea4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
5XX targets that are using per-process pagetables will need to
keep the IOMMU clocks on the entire time because we don't know
exactly when the GPU might touch it. That said there are
occassional depencency issues if the clocks are enabled out
of order. To be certain we should enable the MMU clocks last
and disable them first. Add enable/disable hooks to the MMU
struct to do this cleanly from the GPU pm_resume / pm_suspend
paths.
Change-Id: Ic0dedbad8e2298e55c90b29eed657baa0933ddcf
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Very soon we will be adding support for secure domains and so a bit of
refactoring is needed the GPU IOMMU code:
* Add support for directly probing the context bank device at create
instead of at attach. This makes it a little bit easier to directly
associate a mmu device with a specific context bank.
* Specify the domain type at create time. Add a new domain type
MSM_DOMAIN_USER to associate the user domain with the gfx3d_user
context bank. Also add MSM_DOMAIN_DEFAULT with no context bank
for legacy devices (read MDP4) with only one context bank
to attach to the parent device. Adding a domain type saves us from
having to create N entry points for each domain type.
Note that dynamic domains stay with their own initalization function.
This is because dynamic domains are cloned from the parent domain
so the semantics are too different to try to smash into the generic
functions.
Change-Id: Ic0dedbad41692e776cddc72cda653ae637f9ec77
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Now that the SMMU/IOMMU differences have been resolved the only delta
between the SMMU and the IOMMU address space implementations is the
actual address space allocation which we can work around by assuming
the caller doesn't want address generation if they specify the same
start and end address (i.e. 0).
With that optimization we can get rid of the address space
sub functions and a bunch of otherwise duplicated code.
Change-Id: Ic0dedbaddef0fcd3a8f39e30f95c71245d84f111
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Finish consolidating the MMU map and unmap operations into a single
function. By passing in the meta token to map/unmap the specific
SMMU operations can make a local decision as to which function to
call.
Change-Id: Ic0dedbad52aac6ed1317411b2667755794d1818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For all intents and purposes the mmu ->map function has used a
scatter gather list for some time. Drop the pretense and just
make both the SMMU and IOMMU flavors use the sg flavor of their
respective iommu API functions. As a result we can drop the
map_sg hooks in the SMMU driver and get rid of a considerable
amount of re-invented wheels in the IOMMU driver.
Change-Id: Ic0dedbadc4724c8ae389892fb85610435c5c08cf
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Pass the bo flags all the way down to the iommu map code and
translate into the IOMMU flags right before mapping. This crosses the
streams a bit by moving BO level knowledge all the way down into the
MMU driver but it removes IOMMU specific knowledge from the address
space level which will be important when the address space code for
the GPU and the display are merged into one.
Change-Id: Ic0dedbad256f8986658bbe50fc2e2bd4051b7a7c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
copy_from_user_inatomic() is actually a local function that returns
-EFAULT or positive values on error. Otherwise copy_from_user() returns
the number of bytes remaining to be copied. We want to return -EFAULT
here.
I removed an unlikely() because we just did a copy_from_user()
so I don't think it can possibly make a difference.
Change-Id: Ic0dedbad3437020c12053b6d93276a4dd24a577a
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 21c42da18ef128ca8fb4cc4ead888f5c61e3916a
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[jcrouse@codeaurora.org: fix minor merge conflict and checkpatch errors]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For backwards compatibility the counter group list has some built
in gaps that return NULL when queried. Make sure that all the
functions that query the list are able to handle a NULL pointer.
Change-Id: Ic0dedbadd10ccf3a3b9b1f1b035a46a4f7ee8493
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add sync operations to give the user more control
over the behavior of cached buffers.
Change-Id: Ic0dedbad67e19a6b30b2cc5f6b2c7bbe52c2b708
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
DSI display list sequence should be consistent with device tree, so use
list_add_tail instead of list_add to insert dsi devices.
Change-Id: I11d14d663c59c8ee0d1da280f42d9315e12c2a65
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Clock recovery needs to update HDMI clock in order to
compensate the clock drift, so add a connector property
named as PLL_DELTA to support it. Meanwhile add a node
in debugfs to expose this functionality.
CRs-Fixed: 2015827
Change-Id: Ifdc7134b33102f112a8e3c659fae6a017ff11461
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
If the user provides a profile buffer identified with a buffer type
MSM_SUBMIT_CMD_PROFILE_BUF, then the driver records the kernel clock
time and gpu ticks at the time of cmdstream submission, and the GPU
records the ticks just before the start of the cmdstream execution and
right after the end of the cmdstream execution.
Change-Id: Ic6298ec5919b18e976ae089ffb0860b8165ce4f3
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Currently both sde_crtc_atomic_begin() and
sde_crtc_atomic_flush() add the CRTC state event
to the cached sde_crtc->event.
This has a potential NULL ptr issue in the
case of vblank event firing in between sde_crtc_atomic_begin() and
sde_crtc_atomic_flush() because the upstream DRM vblank API
send_vblank_event() doesn't consider the case when the VBLANK
interrupt could have already freed any pending vblank events.
Remove the caching from sde_crtc_atomic_begin() to avoid this
condition.
Also make sure that a page_flip event was indeed submitted before
signaling the complete_flip() by setting a PENDING_FLIP flag right
after HW flush.
Change-Id: Ib201d2851e57bf22ec1f00814fc2e4dd2f35bfa1
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
If the panel is using bridge chips, such as ADV7533, it doesn't
have to set up backlight.
Change-Id: I014d697f81ecf1748ade2c40353ffdf9ff7c3669
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Panel pin control is not mandatory for all of the DSI panels.
If the panel is using bridge chips, such as ADV7533, it doesn't
have to configure the panel pin controls.
Change-Id: I48d862a9c67d52c0ed8c3c0309b0ff56d13e97f4
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
This register is not accessible by CPU for certain TZ, trying to read it
will cause CPU hang.
Change-Id: Ica1b18db2c3cc2c9bacfdbd4c5eb1e2e172ade33
Signed-off-by: Kasin Li <donglil@codeaurora.org>
