* Enable DU using DT on marzen/r8a7779, lager/r8a7790 and koelsch/r8a7791
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUWBRRAAoJENfPZGlqN0++Pm0P/3Qa+X8o4kAZETi+ER+Q7s/B
d0EGNAw/1b/Si7D2SpftRHvHx5TDL2QiU0QIAPWAcd4u1NJxaYP/SDwRETGQnHbV
TsL25mASYNByP6DXTrBJneiDS5U88DwVP5q5FW9WEkvIbmtzbxTe/7OnSPAjhxl0
83kXATiHwdRct4KYLW8ngNhaY/9OUjrL+wZ8ffN/dM0EpSyixXK5bHmWLFC5/HGY
D8b+zW/NTSBOYTk1OR6QSlp/eGmjRCG2UJn4toHWKse2defxZ/hyTUas4ysgDXzC
gsWT96yLwmueTRcSBglkKGFbPukWcyKPt7sRphtZlTYbJmpS0ncBTfC2s0+Jv2RR
VDpeAmB6NXQ5L7Ck51ryt4A8kX88uOgHrmcz+NGJadNE07TZgLJBLDf6aSjDsytr
NIZq7RFNK975Qv3QldQJX4PYmqcWJMI5WDPnm2buzZsKHkjQrpKIicAiSlwzJX/9
4SeCF2yrZuJJVnJwit8gOvvBHq5ORQrumAs1xrPQiu570p+6jBjjJ5v4sDvuF5UY
nXfMTUGrNYe8JSxjf8NTmXJX8DRKSLq0tGcHbzajvKVzuy8Gp6+yFNkrqzQj2HK6
dy4TLtuvMk5JB4E5Q22xdYYV4TorO28qiuGoGDOOwIx6+940MdY/ucE2Z4i4M2R7
/NZJCpITds6HxVZJWAKo
=m0Ov
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-du-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Pull "Renesas ARM Based SoC DT DU Updates for v3.19" from Simon Horman:
* Enable DU using DT on marzen/r8a7779, lager/r8a7790 and koelsch/r8a7791
* tag 'renesas-dt-du-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: koelsch: Enable DU device in DT
ARM: shmobile: koelsch-reference: Remove DU platform device
ARM: shmobile: lager: Enable DU device in DT
ARM: shmobile: lager-reference: Remove DU platform device
ARM: shmobile: marzen: Enable DU device in DT
ARM: shmobile: dts: Add common file for AA104XD12 panel
ARM: shmobile: r8a7791: Add DU node to device tree
ARM: shmobile: r8a7790: Add DU node to device tree
ARM: shmobile: r8a7779: Add DU node to device tree
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains the serial port numbering fixes that are required for the
serial port numbering to stay the same with or without the serial core
making use of the aliases defined in DT.
eMMC is also fixed for TN7 and Roth boards which were using the wrong
regulators.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJUZNbZAAoJEN0jrNd/PrOhZugP/2SABzzEa1EwAwE0ksM/Z47x
MYDGUQ7nKuagGNwdHsQPEf+JXLADS1eOzdoQ187SaJdSt0DmbOzoU2IbG9b6Rm4j
31Al6XL2PdyDOeopMSbrwLHh7+HVhaW7TEQcCMqDJEEgsJIWY0sLuuDLLirpMoaO
oPD9anXAlVYhcDN8bPdW0gUMrZOGU9rB+q1jTj9kW1qX9xsNHb05WvLiZOwV032d
Hw0/q/BJ/MzoqXT/Z2UrIPpgcL9xnVw3NUPqE+dCXoAGRSsG6ggue+9TDAVyU7Xw
Fg4Hwm/qwnk1lAKvMgGw+fjLd/gUdIuo2kAg5sY2tGo+HTbgMMIz2LlXoz3gmx8/
XnBIKnCqv79kVIyRsOVYLXWrPJx5Ns8rMWXxM/SnD6hPNsudE/rr5dBHP+vS40AU
V/ty6G7BME1LM99h76Ixoaaw5ojjYLPdTb30SEKePKLsY+8gYh6up5Fuo1SdENlv
sIuQR1R7pGbsmshfMd5+xNH55QEucYD/IKz59Zc5+fZJBMEViMH2Q2NIsLYCsO1C
oSN3ck9Gwan2PrEV42uVOHPoQdqta8ZGm02Fl3pJb/2W04/KB3ahdCcPbBI9UGol
zR1EPbUlEiLN1Fczw7gy0/zrFO2Cq4VzwuHZgwiQvsxY8K2ChmsvloBnt9Rpj+VS
Xqbno7ENFXdRiIMWoIn0
=ick3
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.18-fixes-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into fixes
Pull "ARM: tegra: Device tree fixes for v3.18-rc5" from Thierry Reding:
This contains the serial port numbering fixes that are required for the
serial port numbering to stay the same with or without the serial core
making use of the aliases defined in DT.
eMMC is also fixed for TN7 and Roth boards which were using the wrong
regulators.
* tag 'tegra-for-3.18-fixes-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: roth: Fix SD card VDD_IO regulator
ARM: tegra: Remove eMMC vmmc property for roth/tn7
ARM: dts: tegra: move serial aliases to per-board
ARM: tegra: Add serial port labels to Tegra124 DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Correct IIC0 parent clock on r8a7740
* Correct SD3CKCR address to device tree on r8a7790
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUYrybAAoJENfPZGlqN0++V0EP/1VvilCY1UkP4JG142J9GLKl
8V4H30OfVWr9m9O6LPEwOB/qkl9L6mlyu+oxTi1VI+96542IREfYz/REdy3HmgS2
zD7SEMikoqNbuPfjimonBSbtjRvNLrdcNBjrP9u0pJEZYmGBJelNWxTHAsp6fxDy
6nG+/hiNO3i7hyMaZwsYB+5E+9itJkSv4YOS9bh0IAM+WIMN+VasrMSGu9ZKUCT/
f2zcy2xLR/Zmd2ad6zpfFXDznO6C2vBfGg+fZ97K7H5mkSdkpSR5vYwxVWQY+49L
iTlevIi9E7ubp3QIgiSDy9qLAmWxL6wGm4Utj90c+jSKeLPd9NTmGAz0bIjVSYND
b8pmdww3dbYsxyqsWbYlscpYwxN83jynEQx3ZU0dCEA9X7o7SfkQpZlhw/qkNAIu
3iwEqNbrLLlz9nyl7lMFRUPGcn6pugd5ylq6zhfHR9cRRuMAjkkA/1iTEt4kPXSq
6wFLArgNSID9ood0mpuVzp0xWmqY9XsxwYQJLfIE53W8CatWP/HAWAEBiunCJVTg
p0A1WbRrVL0GIQ8QEOjfAo+a0WF0gaiT4Xr66tq6U0o0JwSXr7fws77cl82GXyol
m7AKJ+lzPS2RQg0DdjZAQ1OkA9laQmXtQb44a6OipMw2JdM3oG5yvK0IAb+sxjh1
mOiUw0Zggyf/L+PAxeKJ
=Du2A
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Renesas ARM Based SoC DT Fixes for v3.18" from Simon Horman:
* Correct IIC0 parent clock on r8a7740
* Correct SD3CKCR address to device tree on r8a7790
* tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock
ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the RTT and GPBR devices and specify the general purpose register
used to store the current time.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable the RTT and GPBR devices and specify the general purpose register
used to store the current time.
Enable wakeup on RTT event on the shutdown controller device.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
at91sam926x, at91sam9g45 and at91sam9rl SoCs all have at least one RTT
block.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add rtc support to the at91sam9rl dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
During the submission of these new sama5d4 files, the GPL notice mentioned the
device tree as a library, which is not really accurate.
Fix all these library mentions to reflect the fact that it's actually just a
file.
Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
A fix for the A31 dma controller that requires the AHB clock to be parented to
PLL6 in order to operate.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUa8ABAAoJEBx+YmzsjxAg2HoP/3UCG+58cnEAQTFwVsroU4MT
f91pcPounpGXPmZupQCs/aEHQKSVOEzn2EnHSZQb3I9XEezVKqJHgwm/BlsCHkL0
8WCnG/72p/HoWyMDPr2EPIa1s5oS5wqG0V7rTztTndQI/jHXqPqOdhkicF2n4B7D
hLTxIGeCXA8yh6B3pXF4SdvJEd/I63gcQexzxOJ4HSEsEyGExeTSWwNJqfkl+T2f
ZdyKvvgDbqfgwM6eOX8R6n9RET1Rxtm8NBVdSB2ruuixSV3TT3nYofOgdFddSMtf
WpNUwbVBKE/J0r+NpSQ44E4hFR8W99ieXH3HCPn1+GjHWvFALC0cZTPd6NgIkpBy
uEuAVShJd02Z0JzeTVW7DaCyDgW0QRV7BhBazKuCMppbv8eNR8CbqPe44iY1tmmP
+m7b3HURgs9I5FAwDMrScSPfyH7+tALdTmsXJdBk273cXptRoJAPe+N5G02WLjSk
wo1sW86XcG02Jd20lbdubjsSL5b6pD5pu8zjKISZZI/1kH8m8delvH+ObCjsvaC8
DWELzxRqE6hsi6HjWmkakCZvydn9P0Te5AjX/kzonpqGN30Kzwkk902K3gI/6fT1
5bE9QcC435ckeWLGPMRkLSadHIaUMrmlzt0X4ZN9Evu8F4heT/HqT9wApx8dCwuo
AkcVwXY7Kzxs6dICuojB
=SmW6
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Merge "Allwinner fixes for 3.18" from Maxime Ripard:
A fix for the A31 dma controller that requires the AHB clock to be parented to
PLL6 in order to operate.
* tag 'sunxi-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There is a macro for the irq type.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Explicitly set the dr_mode for the dwc3 controller on the
Snow board to host mode. This is required to ensure the
controller is initialized in the right mode if the kernel is
build with USB gadget support.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The LEDs on the kzm9g board are labeled using upper-case characters.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LEDs on the koelsch board are labeled using upper-case characters.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The IIC nodes used the generic compatible properties only.
This causes the driver to fail when using Standard Speed, as the
operational clock is driven by the 104 MHz HP clock:
i2c-sh_mobile e6820000.i2c: timing values out of range: L/H=0x208/0x1bf
i2c-sh_mobile: probe of e6820000.i2c failed with error -22
Add the SoC-specific compatible property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The IIC nodes used the generic compatible properties only.
This may cause the driver to fail when using Standard Speed on IIC
masters where the operational clock is driven by the 130 MHz HP clock.
Add the SoC-specific compatible property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Koelsch I2C2 has 400kHz settings,
but, ak4643 audio codec chip which is connected to I2C2 can't
work such frequency.
Fixup I2C2 clock frequency to 100kHz.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Lager IIC2 is using default clock frequency,
but, ak4643 audio codec chip needs 100kHz
This patch clarifies IIC2 clock frequency as 100kHz.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable usb1 on Google Chromecast which is connected to micro-USB
plug used for external power supply, too.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds nodes describing the Marvell Berlin BG2CD USB PHY and USB. The BG2CD
SoC has 2 USB ChipIdea controllers, with usb0 host-only and usb1 dual-role
capable.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Enable the 2 available USB PHY and USB nodes on the Marvell Berlin BG2Q
DMP.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q
SoC has 3 USB host controller, compatible with ChipIdea.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add nodes for I2C controllers A,B,AO, which are available in both
Meson6 and Meson8.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
Following Arnds review comments, update the miphy365 to follow the
common convention of naming the phy node names as phy@addr.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
At the moment we don't take a reference on some core interconnect
clocks which means when CCF turns off unused clocks the SoC will
hang. As a temp soltuion we will boot with clk_ignore_unused
parameter for all b2120 boards.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
