Add programming the PLL_CAL_L_VAL register to the fabia PLL
set_rate sequence. This is required on MSMCOBALT v1 as a
workaround.
CRs-Fixed: 1016938
Change-Id: I298acf633228b2c565736bf7bfd446d96f4e1983
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Currently we don't support having both CONFIG_DEBUG_RODATA
and CONFIG_FORCE_PAGES enabled at the same time.
Update the dependencies for CONFIG_FORCE_PAGES to enforce
this.
If there is a need for read only support with
CONFIG_FORCE_PAGES enabled then enable
CONFIG_KERNEL_TEXT_RDONLY instead of CONFIG_DEBUG_RODATA.
Change-Id: I9ee1732ed0673edc7272d32469d08133fba9637f
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Port support from 3.10 for retrying cma allocations
to 3.18 to help resolve cma allocation failures.
It was observed that CMA pages are sometimes getting
pinned down by BG processes scheduled out in their exit
path. Since BG processes have lower priority they end up
getting less time slice by scheduler there by consuming
more time to free up CMA pages.
Also when a process is being forked copy_one_pte
may create copy-on-write mappings, when this is done
the page _count and page _mapcount are each
incremented sequentially. If the process is context
switched out after incrementing the _count but before
incrementing the _mapcount then the page will appear
temporarily pinned.
So instead of failing to allocate and directly
returning an error on the CMA allocation path we do 2
retries, with sleeps, to give the system an opportunity
to unpin any pinned pages.
Change-Id: I022a9341f8ee44f281c7cb34769695843e97d684
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
Signed-off-by: Liam Mark <lmark@codeaurora.org>
While force mapping regions as page, do not go for 1GB
block mapping.
Change-Id: I85ca7046626048acb7a138dc174dc40efbba4ac9
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
The provision to map 1GB block, gives a problem during
dma_contiguous_remap when it attempts to remaps the dma
buffers into 4K. During this attempt to remap dma buffers
it overwrites pgd mapping for 1G block, thus leaving an
unmapped hole.
Managing remapping of dma regions with 1G block mapping is
difficult hence avoid mapping 1G block and switch to
SECTION_SIZE mapping (2MB) when memory region overlaps
with dma buffers range.
Change-Id: I2aa4119b3aeb328a2b95cf22656d2ec36012716f
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
bonding and TC drivers (sch_multiq) are required
for fast session transfer feature.
CRs-Fixed: 1001827
Change-Id: I08ee482ddc6c189241a69452fb12335d1ffb626f
Signed-off-by: Maya Erez <merez@codeaurora.org>
In cases where source ep or dest ep is not valid, descriptor
memory allocated for frag skb's is not freed. Make a change
to free the memory in such error cases.
Change-Id: Ie15c48ae1bb34e304795607a09c753360eb015ec
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Make changes to use consistent function names across v2 and V3
during SSR functionality.
Change-Id: Ib9c79f4795d0be9ca00b3cda984ed89b61e58b02
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Enable v4l2 video driver on msmcobalt for decode
and encode sessions.
Change-Id: Ibda63abad6a469c0a5f738c51ee1e740d0f1ce7a
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Enable VMEM node and configure the
size as per msmcobalt.
CRs-Fixed: 1008076
Change-Id: I8bbb827e6fcddb12bf452279f5f7d60b614c2915
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Common log driver can be used to register entries for memory dump table.
Change-Id: I75be0d467c8f7c2db854987598770f9798688e51
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Set MSM_DCC config to enable support for Data Capture and Compare(DCC)
device.
Change-Id: Ibc2de3c142b8df4ac86e4628199726750f19dac3
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to allocate memory for CPU scan dumps. This momeory can be
used to save CPU scan dumps at the time of a crash.
Change-Id: I9d644f18882729d187075e885bc2e8c02c5caf36
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add node to add support for Data Capture and Compare (DCC) device on
msmcobalt.
DCC block can be used to capture user programmed memory mapped registers
or to run CRC on user programmed memory region.
Change-Id: I1d302e51693315998d915ca44f739fb58ef9e4a5
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Adding clock rates to camera node instead of statically
reading from sensor driver so that clock names and
rates can be read from camera node using common software on chip
API and if needed it can be overrided with the values obtained from
userspace sensor drivers.
Change-Id: Icf950194191cbd0887740d692bb88cc650430fb8
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
If the size of captured data oversteps over SRAM boundary then
it causes corruption of configuration data. Add boundary check
while programming configuration linked list in SRAM, to avoid
this problem.
Change-Id: Idd33f53560585fdbfee4d3822fd93d6f3a365e17
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Acorrding to function really_probe, the ENODEV will not throw
any error message. Changing ENODEV to EINVAL to notify error
message if probe fails.
Change-Id: Ia3187fadd4f0073e5e141595810bb8b3c7aab429
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
TZ image which has registered SCM_SVC_DISABLE_XPU sevice maybe used by
none-dcc-xpu device. Update the xpu check logic to fix the probe
failure issue.
Change-Id: Id2b38d93e7c12648292546592144eda1e82d76be
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to request TZ to lock and unlock DCC XPU.
DCC XPU is unlocked before accessing DCC and is locked back again after
configuring DCC.
Change-Id: I8815f65551df0b80f7ecdcaa338a50db8d9b04f5
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Tsens controller wont be able to send any temperature data in RUMI.
This will block LMH driver in HLOS during profile switch.
Disable LMH driver probe for RUMI to avoid this profile switch.
CRs-Fixed: 1015361
Change-Id: I729af5235109cf8b09d4c89a339a4b4f14926d26
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Use readl_poll_timeout instead of readx_poll_timeout because
readl_poll_timeout already uses __raw_readl to read IO register.
Change-Id: I86d93bc63cf3282e360eed29732a708ee02cf6df
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Currently user needs to provide base, offset, and length to program
a configuration in DCC.
To simplify user input, this change requires user to provide just start
address and length. Driver is going to calculate most optimized base,
offset and length to configure user request in SRAM.
Change-Id: Ic1b7b2d4d4ed4baa9e8d33a2b60c10d2e799b211
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to request RPM to turn on/off DCC SW trigger.
This request can be used to enable/disable DDR training data verification
before DDR frequency switch.
After receiving enable request RPM assumes that DCC is configured in CRC
mode to verify DDR training data. Hence it starts to send SW trigger to
DCC to run CRC on configured data before DDR frequency switch.
Change-Id: I491bc3e41e11a5366162c65907f41f7cbcdd7809
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
In CRC mode DCC can perform CRC on configuration data or system memory
after receiving SW or HW trigger.
Change-Id: Iab0a6ffa92ef6e311054756cfe85d1b2b91743c9
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Fix bug due to use of uninitialized 'prev_off' variable.
Change-Id: I773f64209b395eb9f2fc82a53d4a2f1b79b081eb
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
DCC (Data Capture and Compare) is a DMA engine which is used to save
configuration data or system memory contents during catastrophic failure
or SW trigger.
It can also perform CRC over the same configuration or memory space.
Change-Id: Ic8a804250ab8b7ac501bd186d2e6f7506bb9b21a
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add the necessary frequency configuration to the OSM and CPUfreq
device nodes to allow frequency scaling of the Silver cluster in
msmcobalt to SVS Fmax.
Change-Id: I8153e1c2ad9cb320a4c116593b15898dbe2f6ca2
CRs-Fixed: 1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Raise the VDD_APC0 and VDD_APC1 CPR floor voltages to be equal to
the Nominal ceiling voltage on CPR revision 0 parts. Also, increase
the number of supported fuse combos to 8, to support up to 8 CPR
revisions using a single speed bin. This ensures stable operation
on some msmcobalt CPR revision 0 parts that cannot operate
reliably with SVS2/SVS voltages and has no impact to CPR rev 1 and
greater parts.
Change-Id: I6913a168596b34f527f689360f93fdf15b7d2f10
CRs-Fixed: 1014782
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The pipe format enumeration is not accounting for multi-rect on the
pipe list. Update the loop enumerating formats to account for multiple
rectangles per pipe.
Change-Id: Ief1980e2888525434e876f7cec4357403ca20cb1
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Fix macro name so CONFIG_SCHED_HMP_CSTATE_AWARE=y to take effect.
Change-Id: I0218b36b2d74974f50a173a0ac3bc59156c57624
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Tsens controller wont be able to send any temperature data in RUMI.
This will block LMH driver in HLOS during profile switch.
Disable LMH driver probe for RUMI to avoid this profile switch and
lock up.
CRs-Fixed: 1015361
Change-Id: Id54c09e0cf2c3701c10c71d6688417d3f5d4c08e
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
This reverts commit 28f67e5a50 ("sched: set HMP scheduler's
default initial task load to 100%") since 100% of init task load
makes too much of power inefficiency on some targets.
CRs-fixed: 1006303
Change-Id: I81b4ba8fdc2e2fe1b40f18904964098fa558989b
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux)
which allows the pixel clock to be either sourced out of the VCO clock
or the bitclock. In the current code, the ops for this mux clock is
overloaded incorrectly which results in the pixel clock being always
sourced out of the bit clock. Fix this by using the default mux clock
ops for this clock.
Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In glink_core_channel_cleaup there is a race condition while
traversing the channels list. This change holds the xprt
channel spinlock during the list manipulation.
CRs-Fixed: 988266
Change-Id: Idcff59ca1483fd98173255d6258e6771d91dec19
Signed-off-by: Chris Lew <clew@codeaurora.org>
This reverts commit 7b1a1d2263 ("defconfig: enable msm serial console
on msmcortex perf config").
We do not need this change since USB issue is fixed. No longer need
console to connect or disconnect USB.
CRs-Fixed: 1015006
Change-Id: I49154af38f0c59f6add8a38ebbc06f7dcfc85373
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Enumeration for writeback is not properly done because not all
information from device tree has been retrieved before setting up
supported formats. Moved this call until all data has been retrieved
from device tree and hw pre initialization.
Change-Id: Id228bf7ec564669fa8e9e739e27052de0133cc4d
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Data Capture and Compare (DCC) is a DMA engine, to capture or to
perform CRC over configuration data or system memory.
Add ids for DCC registers and sram data.
Change-Id: If76ef1325b1be623626742b0f0172a1675f21d63
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Fix the memory leak in common_log_register_log_buf() function
when registering log_first_idx with the memory with dump v2 driver.
Also use kmemleak_not_leak when msm_dump_data_register() calls
are successful to ensure that kmemleak doesn't report it as a memory
leak.
CRs-Fixed: 832905
Change-Id: I36eaeebf821f64dd7503ec823aca3c7aec846bd0
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Allocate memory to dump RPM CODE RAM at the time of crash.
Change-Id: I5062d65a095538a508944315e6cc06f430382bf5
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Allocate memory to dump VSENSE registers at the time of crash.
Change-Id: Ibd896873bc40b723071c66ca7cf1a4bc9b38ad5e
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Register for dumping 4KB of memory to dump PMIC
registers which can be parsed in case of device crash.
Change-Id: Idbf26d6241ab9a87e4dcea42723428289f2a869d
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
This snapshot is taken as of msm-3.10 commit:
78c36fa0ef (Merge "msm: mdss: Prevent backlight update during
continuous splash")
Common log registers the kernel log buffer address with the
memory dump driver so that the __log_buf can be collected from
ramdumps without the need of an external System.map file.
Change-Id: Ibeb74ca064e78fe7522e46b3c32bb362082d5d24
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Create and add PCIe resources such as register bases, clocks,
regulators, GPIOs, etc. to msmcobalt devicetree and pinctrl
devicetree.
Change-Id: I7a41ed6dd0f78cba140a15661d44b2f6c2745e39
Signed-off-by: Tony Truong <truong@codeaurora.org>
Enable MSM PCIe bus driver in defconfig for msmcobalt.
Change-Id: I44ece35ed1d8dda4d8139dfb54adc7a2e9c49383
Signed-off-by: Tony Truong <truong@codeaurora.org>
Some msmcobalt PCIe configuration registers have different
offsets than other chipsets. Update these offsets so
that PCIe can be correctly configured on msmcobalt.
Change-Id: I42c7f545a48e6a431ccdba062399776e8c1c64f2
Signed-off-by: Tony Truong <truong@codeaurora.org>
