Using a mutex is problematic if the code can run in interrupt context.
In this patch we replace the ufs debugfs synchronization mechanism
from mutex to spinlock, which doesn't go to sleep.
Change-Id: I4e258898ed0ddf5b84d955fabd4354c2d2891c3d
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
WRITE_SAME command is not supported by UFS. Enable a quirk for
the upper level drivers to not send WRITE SAME command.
Change-Id: If3108134ceefbcb9c8585c1b489b4124ffa6b1ad
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
High Speed rate series might always be set to rate "A" if the
vendor doesn't specify any rate during pre-power change notify.
Change-Id: Ied7ce3eba98ffbece97ec06eb6cab8df1d104f52
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This patch exposes the ioctl interface for UFS driver via SCSI device
ioctl interface. As of now UFS driver would provide the ioctl for query
interface to connected UFS device.
Change-Id: I7a5cea8de925dc0ecb6643774321e2c3690c504e
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
[gbroner@codeaurora.org: dropping changes to the following files:
include/uapi/scsi/Kbuild
include/uapi/scsi/ufs/Kbuild
include/uapi/scsi/ufs/ioctl.h
include/uapi/scsi/ufs/ufs.h
which are already included in previous change titled:
'uapi: scsi: ufs: add ioctl interface for query request']
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts and compilation
errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This patch exposes the ioctl interface for UFS
driver via SCSI device ioctl interface. As of
now UFS driver would provide the ioctl for query
interface to connected UFS device.
Change-Id: Ib8301a69550408bfcb5fc85bb9c0498450c8cc31
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Assign a value to 'ret' in order to prevent a compilation warning of:
'ret' may be used uninitialized in this function.
Change-Id: Id10d0e5e8204d233cf4906bc33709d3c012d964f
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
In this change the default preferences of the UFS vendor
are set to work in HS-G1- 1 Lane, as the enviroment became stable.
Change-Id: I340190d5c6cf4f848f9def7eba8831fb299adadb
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
since two different routines implement almost the same logic of
scanning the ufs clocks, getting the rate of "core_clk" and
setting a vendor timer register with a calculated value,
we should use only one routine to do that in order to minimize
potential errors
Change-Id: I22728295074acfbe4d421996ea9eaa1f29cb3a32
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Sometimes, the device shall report its maximum power and speed
capabilities, but we might not wish to configure it to use those
maximum capabilities.
In this change we implement the vendor specific callback that should
determines what parameters we should use in power change.
It takes into account the maximum capabilities of the device, and
also the pre-defined vendor preferences.
According to both set of parameters, it calculates the maximum power
and speed that are still acceptable by both: the vendor preferences
and the devices capabilities.
Change-Id: I3ef468d3882f3ed9d49a99aa285af4a1f58063a0
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
fix fall through in msm_ufs_link_startup_notify() during PRE_CHANGE,
since we would like msm_ufs_enable_tx_lanes(hba) to happen only in
POST_CHANGE
Change-Id: I91b1134ef7060ee8b8189335d0ef7b5a4f546534
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Fix missing update of ref_clk enable reference count when the
clocks are enabled and also enable shutting down the phy and
device during system suspend.
Change-Id: I7772cd87e0d0528ab5dbe6ea9f09e6d02c86f96c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This change adds a few more options to a user to get a complete
status and statistics regarding the UFS driver, via debugfs
This information includes:
1. UFS Host Controller registers (cat /sys/kernel/debug/ufs/host_regs)
2. hba values (cat /sys/kernel/debug/ufs/show_hba)
Change-Id: Iac60de81a56ed42de72c3a7946a0d2bb5fab2903
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
This patch adds the vendor specific UFS power management support for MSM
platform.
If UFS link hibernate operation is broken in HW, make sure that link
remains active and device in sleep state during the runtime suspend.
During system suspend, keep both link and device in power off state.
If UFS link hibernate operation is working properly in HW, keep the link
in hibernate state and device in sleep state during both runtime and
system suspend.
Change-Id: Ibc5be00eb9d5fd72ed116b887d835a12ed97ae78
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Due to M-PHY issues, moving from HS to any other mode or gear or
even Hibern8 causes some un-predicted behavior of the device.
This patch fixes this issues.
Change-Id: I4540e30703aa1212099b2316e158b09e311c7420
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
UFS devices on msm ufs v1.1 controller fail to change power mode
during initialization. Enable the UFSHCD_QUIRK_BROKEN_PWR_MODE_CHANGE
quirk to make sure the power mode is not switched.
Change-Id: Ie02ae5a2da3604a83828325719eb5edb167ca82e
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Some devices, even though advertises command queuing capability,
may not behave well when multiple commands are queued concurrently.
Disable command queuing for the device to avoid command hangs when
multiple commands are sent.
Change-Id: I7458c081976e96d2a97c8c9544acfd29163d9e1f
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Reference clock is propogated from source to PHY with various
LDO gating logic in between. Add support for enabling these
LDOs and also source reference clock.
Change-Id: I0de6d5d47aff175cd5526b6de2f8e4078cb08316
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
UFS 1.1 specification defines READ_CAPACTIY(16) as an optional
command. Hence, try READ_CAPACITY(10) first, if the device returns
0xFFFF_FFFF as returned logical block address then send
READ_CAPACITY(16) to read the actual device capacity.
Change-Id: I2690d26be967e6be4debdc773100c55ba751aa1f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Modify the PHY power up calibration values according to the
latest hardware specification.
Change-Id: I145dc8d5644c1914bb0fcb9c9b5790cf2b8de367
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
MSM UFS host controller advertises CAP.64AS bit as zero
even though it can adress upto 36 bits.
Change-Id: Ia8edd9ede3cc5e8358775d1efca5451cc3559773
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Some UFS host controllers might advertise that 64-bit
addressing is not supported even though it supports >32-bit
addressing. Add a quirk so that 64-bit is enabled and dma mask
is set accordingly.
Change-Id: Ie17662f55dda1da7d508efb881ac8fb8fa95f15a
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The device-tree probed device for ARM doesn't have dev->dma_mask.
So dma_set_mask() for the device doesn't succeed. The popular trick
for this is - dev->dma_mask = &dev->coherent_dma_mask;
Currently there is no dma_set_mask() call in ufs-pltfrm, but the
forthcoming fix needs proper DMA mask setting in ufs core driver. So
initializing dev->dma_mask as described above is required.
Change-Id: I8428f106ca2d97badb7bf57cbb1d3ee14dddaf7f
Signed-off-by: Akinobu Mita <mita@fixstars.com>
Cc: Sujit Reddy Thumma <sthumma@codeaurora.org>
Cc: Vinayak Holikatti <vinholikatti@gmail.com>
Cc: Santosh Y <santoshsy@gmail.com>
Cc: "James E.J. Bottomley" <JBottomley@parallels.com>
Cc: linux-scsi@vger.kernel.org
Patch-mainline: linux-scsi@vger.kernel.org @ 2013/08/19 19:26
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
In msm_ufs_check_hibern8(), the loop never breaks until
timeout even if the tx_fsm_val is equal to expected value.
Change-Id: I6f5ee6aea2e50ff6c88547d5e651d6cccfd25212
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Qualcomm MSM UFS controller version register (VER) wrongly advertise the
version as v1.0 though controller implementation is as per UFSHCI v1.1
specification. This patch corrects this HW behaviour with appropriate
quirk handling.
Change-Id: Idc99e8504617e7828043e06afdaecb7ddc4218f8
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some implementation of UFS host controller HW might have some non-standard
behaviours (quirks) when compared to behaviour specified by UFSHCI
specification. This patch add support to allow specifying all such quirks
to standard UFS host controller driver so standard driver takes them into
account. Currently only couple of quirks (UFSHCD_QUIRK_BROKEN_HIBERN8 &
UFSHCD_QUIRK_BROKEN_INTR_AGGR) are added but new quirks can be added as
and when other non standard behaviours are found.
Change-Id: Ie8e686bb59e7933a281a4ff189a35c71036b1e92
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
After link startup the phy adapter (PA) layer in Uni-Pro
automatically detects the number of available lanes for
communication with the device. Since it is choice of s/w
to use all the available lanes or a partial of them, it is
necessary to communicate to MSM PHY about the lanes not being
used so that PHY can stop driving them.
Change-Id: I6f005e67a4c0a35dcba0ff186de5817af1b0439d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Add MSM UFS host PHY driver which binds with UFSHCD platform
driver exposing vendor specific operations to initialize the
PHY. Since the controller and PHY are tightly coupled in the
system, some of the MSM specific controller register
configuration is also applied inline while initializing PHY.
Add a new compatible property "qcom,ufshc" which specifies the
UFS host controller on MSM platforms. The UFS controller driver
binds with UFS PHY driver using the phandle reference of PHY
devicetree node.
Change-Id: If695a844d03268151c6c846bdfa6cee8ff84491b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Created a new UFS block device test framework.
This test includes:
- Basic read after write command
- Random buffer length
- Ability to run test multiple times
Change-Id: I06fe7bf7d325037d6039a4acfdfb9c2c8960a435
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Clear the UFS data structures before sending new request.
The SCSI command is sent to the device within the UFS UPIU request.
As part of the transfer UPIU preparation, the SCSI command is copied
to the UPIU structure according to the SCSI command size.
As different SCSI commands differ in size from each other, we need
to clear the whole SCSI command field to prevent sending uninitialized
data to the device.
The UPIU response doesn't always include the sense data and can differ
in size.
Hence, the UPIU response should also be cleared before the transfer.
Change-Id: I9bba619dc884e973a05566e0f975bd8473612644
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Enable the GCC clock driver in the MSM8996 device tree and
update the uartblsp2dm1 serial node to use the correct clocks.
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Drivers that are registered at an initcall level may have to
wait until late_init before the probe deferral mechanism can
retry their probe functions. It is possible that their
dependencies were resolved much earlier, in some cases even
before the next initcall level. Invoke one probe retry cycle
at every _sync initcall level, allowing these drivers to be
probed earlier.
A real world example of how this change helps follows. On the
MSM8974, there are 3 devices that need to be probed in order
for the display driver to be able to probe and bring up a
display panel. These are the gdsc_mdss (a regulator device), the
mmsscc-dsi device (a display clock controller), and the
dsipllcc device (a PLL controller). Here is a kernel log that
shows these devices probing in the wrong order:
[0.503253] mmsscc-dsi fd8c0000.qcom,mmsscc-dsi: Failed to get pixel source. -- [1]
[0.505210] dsipllcc fd8c0000.qcom,dsipllcc: Failed to get MDSS GDSC -- [2]
[0.523264] gdsc_mdss: no parameters -- [3]
Only gdsc_mdss successfully probed at 0.52 seconds. Now without
_this_ change, the current probe deferral mechanism results in
the devices probing at or after late_init:
[9.196006] dsipllcc fd8c0000.qcom,dsipllcc: Registered DSI PLL clocks. -- [2]
[9.357440] mmsscc-dsi fd8c0000.qcom,mmsscc-dsi: Registered MMSSCC DSI clocks. -- [1]
Thus the display can only be brought up after 9.35 seconds. However,
by allowing a probe retry after each initcall level, this number
reduces drastically:
[0.608252] dsipllcc fd8c0000.qcom,dsipllcc: Registered DSI PLL clocks. -- [2]
[0.613758] mmsscc-dsi fd8c0000.qcom,mmsscc-dsi: Registered MMSSCC DSI clocks.-- [1]
Thus the display can be brought up just after 0.61 seconds.
Change-Id: I83d8ac89e591e89e27934c0402449437b61b2124
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
This is a snapshot of kryo l2 accessors driver as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of
kernel.lnx.3.18-151201.)
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Add clock tree support for MSM8996 and MSMCOBALT, and add corresponding dt
bindings header files.
Change-Id: If0281f96ce5dd29b04f190efa1527888bc240bb5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Support added for MSM clock and modifications in the clk framework to use
the MSM clock framework.
Change-Id: Ibbcf0ffbf9d30dde2dcb0e943225ad95dd4e857d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The clock_set_rate_complete even is used to monitor the latency
of the clk_set_rate API, and the clock_state event is used to
add support in debugfs to take a snapshot of all the clocks
present and their current state to ftrace.
This is a squash of the following commits:
1. clk: qcom: Add support to record clock state using ftrace
2. tracing: power: Define clock_set_rate_complete trace event
Signed-off-by: Taniya Das <tdas@codeaurora.org>
PM_QOS_SUM is a new enum type supported in the upstream kernel. The target
qos value for PM_QOS_SUM type is updated as the sum of all the priorities
that are applicable to the current CPU.
Change-Id: I89152db4fbbf08db113b52e6c5fee4aba9b70933
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Send the list of cpus whose qos has been affected along with the changed
value. Driver listening in for notifier can use this to apply the qos value
for the respective cpus.
Change-Id: I8f3c2ea624784c806c55de41cc7c7fcf8ebf02da
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
[mattw@codeaurora.org: resolve trivial context conflicts]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
kernel/power/qos.c
QoS request for CPU_DMA_LATENCY can be better optimized if the request
can be set only for the required cpus and not all cpus. This helps save
power on other cores, while still gauranteeing the quality of service.
Enhance the QoS constraints data structures to support target value for
each core. Requests specify if the QoS is applicable to all cores
(default) or to a selective subset of the cores or to a core(s), that the
IRQ is affine to.
QoS requests that need to track an IRQ can be set to apply only on the
cpus to which the IRQ's smp_affinity attribute is set to. The QoS
framework will automatically track IRQ migration between the cores. The
QoS is updated to be applied only to the core(s) that the IRQ has been
migrated to.
Idle and interested drivers can request a PM QoS value for a constraint
across all cpus, or a specific cpu or a set of cpus. Separate APIs have
been added to request for individual cpu or a cpumask. The default
behaviour of PM QoS is maintained i.e, requests that do not specify a
type of the request will continue to be effected on all cores. Requests
that want to specify an affinity of cpu(s) or an irq, can modify the PM
QoS request data structures by specifying the type of the request and
either the mask of the cpus or the IRQ number depending on the type.
Updating the request does not reset the type of the request.
The userspace sysfs interface does not support CPU/IRQ affinity.
Change-Id: I09ae85a1e8585d44440e86d63504ad734e8e3e36
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Conflicts:
kernel/power/qos.c
QoS add requests uses a handle to the priority list that is used
internally to save the request, but this does not extend well. Also,
dev_pm_qos structure definition seems to use a list object directly.
The 'derivative' relationship seems to be broken.
Use pm_qos_request objects instead of passing around the protected
priority list object.
Change-Id: Ie4c9c22dd4ea13265fe01f080ba68cf77d9d484d
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
[mattw@codeaurora.org: resolve context conflicts and extend
struct modifications to additional affected users]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
include/linux/pm_qos.h
This change enables some regulator and qpnp drivers.
Change-Id: Ic66cb1e9ed2d73a4f3f15b5bae0895c3c0aae808
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Being able to write to spmi registers via userspace is required
for quick debug and development. Enable it.
The regmap framework uses dev_name to create debugfs dir names.
So update the spmi devices to have proper names.
Change-Id: I8a5da203b212df9a7f1410e3fcf6ee7b429856b6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
struct pmic_arb_irq_spec serves no real purpose. It is used only
in the translate function and the code is much cleaner without it.
Change-Id: I4daae954b8e01b33a9c7f5a343a31c15b4787382
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
PMIC interrupts each have an internal latched status bit which is
not visible from any register. This status bit is set as soon as
the conditions specified in the interrupt type and polarity
registers are met even if the interrupt is not enabled. When it
is set, nothing else changes within the PMIC and no interrupt
notification packets are sent. If the internal latched status
bit is set when an interrupt is enabled, then the value is
immediately propagated into the interrupt latched status register
and an interrupt notification packet is sent out from the PMIC
over SPMI.
This PMIC hardware behavior can lead to a situation where the
handler for a level triggered interrupt is called immediately
after enable_irq() is called even though the interrupt physically
triggered while it was disabled within the genirq framework.
This situation takes place if the the interrupt fires twice after
calling disable_irq(). The first time it fires, the level flow
handler will mask and disregard it. Unfortunately, the second
time it fires, the internal latched status bit is set within the
PMIC and no further notification is received. When enable_irq()
is called later, the interrupt is unmasked (enabled in the PMIC)
which results in the PMIC immediately sending an interrupt
notification packet out over SPMI. This breaks the semantics
of level triggered interrupts within the genirq framework since
they should be completely ignored while disabled.
The PMIC internal latched status behavior also affects how
interrupts are treated during suspend. While entering suspend,
all interrupts not specified as wakeup mode are masked. Upon
resume, these interrupts are unmasked. Thus if any of the
non-wakeup PMIC interrupts fired while the system was suspended,
then the PMIC will send interrupt notification packets out via
SPMI as soon as they are unmasked during resume. This behavior
violates genirq semantics as well since non-wakeup interrupts
should be completely ignored during suspend.
Modify the qpnpint_irq_unmask() function so that the interrupt
latched status clear register is written immediately before the
interrupt enable register. This clears the internal latched
status bit of the interrupt so that it cannot trigger spuriously
immediately upon being enabled.
Also, while resuming an irq, an unmask could be called even if it
was not previously masked. So, before writing these registers,
check if the interrupt is already enabled within the PMIC. If it
is, then no further register writes are required. This
condition check ensures that a valid latched status register bit
is not cleared until it is properly handled.
Change-Id: Ie05845b692a151c39943aa3e2aad6bcae4194d83
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
irq_enable which is called when the device resumes. Note that the
irq_enable is called regardless of whether the interrupt was
marked enabled/disabled in the descriptor or whether it was
masked/unmaked at the controller while resuming.
The current driver unconditionally clears the interrupt in its
irq_enable callback. This is dangerous as any interrupts that
happen right before the resume could be missed.
Remove the irq_enable callback and use mask/unmask instead.
Change-Id: I58695ae0c4905a699003d35498dc36c2a947f3f0
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
We see a unmapped irqs trigger right around bootup. This could
likely be because the bootloader exited leaving the interrupts
in an unknown or unhandled state. Ack and mask the interrupt
if one is found. A request_irq later will unmask it and also
setup proper mapping structures.
Change-Id: Icc2fc4f1bd9b3333e5856fce2daa5ba2b69e9a87
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current driver disables/enables the ACC bit when any interrupt
in that peripheral is being masked or unmasked.
However, the ACC bits were meant to be disabled and enabled when
all interrupts in that peripheral are disabled and any interrupts in
it are enabled respt.
The driver ends up masking the peripheral (i.e. all the interrupts
in that peripheral) if any one interrupt in that peripheral is masked.
There could be other interrupts enabled which will not trigger after this.
Fix this by changing the driver to disable or enable when all the
interrupts in the peripheral are disabled or when the first enable of an
interrupt in that peripheral happens.
Note that we will need to keep track of the enabled interrupts for an
apid. There are other things like ppid and owner information tracked per
apid. Introduce a per apid structure to track all the three.
Change-Id: I256546a7a4683a463beb6d0eb360a0edd4e5c11d
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current driver uses a mix of radix tree and a fwd lookup
table to translate between apid and ppid. It is buggy and confusing.
Instead simply use a radix tree for v1 hardware and use the
forward lookup table for v2.
Change-Id: I74e1dc0c3dbbf2b311786af7d80a9d4810d510d7
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
