Add support for TX path COPP calibration according to
app type configuration
CRs-fixed: 1015476
Change-Id: I0bcbfadb0c1a22529863a5c4b8cc5c53a1028915
Signed-off-by: Derek Chen <chenche@codeaurora.org>
start and end must be page aligned while calling
flush_tlb_kernel_range else the last page may get
missed while invalidation.
Change-Id: Ibaab202c47a475623e197a13191b2fed638ce20b
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Correct the camera dtis place to support multiple chipset
version for msmcobalt skuk device.
Change-Id: I20e12bc1597ad15cb3dc9c3ef18d81d039931e07
Signed-off-by: Wei Ding <weiding@codeaurora.org>
The ramdump driver uses the device pointer during ramdump read.
This change passes in the device pointer for memshare during
ramdump create and moves the call to the probe function.
CRs-Fixed: 1079523
Change-Id: I687696dbedfa0ce7e6053d70291a7beb6f81f82e
Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
Modify the clock_gcc dummy clock to use the real clock controller for all
global clock controller clients.
Change-Id: Iac989d3c9312654b599d8299206e5478ca454861
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add IMEM PIL entry to save relocatable address of images
loaded by PIL.
Change-Id: Ie09c8ae431cc7da4c8cd745d9c6d018e6a256158
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Add IMEM PIL entry to save relocatable address of images
loaded by PIL.
Change-Id: I79acd047c7e414ed19a2f992f8ff801b63c8a2ad
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
This reverts 'commit 7112993181 ("input: touchscreen: synaptics v1.1")'
This change is not needed in 4.4 kernel.
Change-Id: I89ab8f353bc04bc0a04d5f5a6993e8e8e5ebbd2e
Signed-off-by: Abinaya P <abinayap@codeaurora.org>
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
Currently, there is a delay of 20msec before raising OTG
current limit, which may be too long for some OTG devices and
cause unexpected issues.
Change it to 1ms or 2ms per HW timing.
Change-Id: Ie09a65e7974e2412af4add3b6f1e0aa20ee4a34b
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Add support to do initial configuration for alpha plls and votable
alpha PLLs need to have the fsm mode enabled as part of the
initialization using flag 'SUPPORTS_FSM_MODE'.
Alpha PLLs can support two kinds of input signals, normal and latched.
The normal input is directly passed to the core, while the latched input
requires a latch and acknowledge sequence to be performed for the
changed input to propagate.
Alpha PLLs can support dynamic update with both kind of input signals.
The ones which support this using a latched interface however need to
follow the latch/wait-for-ack sequence to be performed when the rate
changes. Mark these with a new flag 'SUPPORTS_DYNAMIC_UPDATE' to handle
this as part of clk_alpha_pll_set_rate().
PLLs could require post div to be set at runtime, add a vco_data which
could be used for these settings.
Change-Id: Ia0b9a2a52a3b33b7b68409c19c460d717eb5c1e2
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
As per the hardware documentation, PFM needs to be disabled for
LAB regulator during slow start. When the display is turned off,
PFM needs to be disabled with the default current limit. When the
display is turned on, after VREG_OK interrupt fires, PFM needs to
be enabled after overriding the current limit. Add support for
it. Currently this is required only for pmicobalt.
While at it, fix the current limit configuration for LAB
regulator.
CRs-Fixed: 1024407
Change-Id: Icb3781ca31dd8474cfca077c52593dc69d011127
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Set LAB's precharge time to max 500us to optimize the precharge
behavior as suggested in the hardware documentation.
CRs-Fixed: 1084297
Change-Id: I118f4254686caf498087847916b7710662ab31e7
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently, some properties in LABIBB regulator driver are having
prefix "qpnp" which is not reflecting the vendor. Change it to
"qcom" to reflect the vendor name correctly and also match with
other DT properties.
CRs-Fixed: 1071971
Change-Id: I182dddc29f3d7c7b449b56ac7fb84e74061cf3a4
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
For LABIBB peripherals in pmicobalt, bootloader configures
LCD/AMOLED mode and SWIRE control based on a GPIO selector.
Hence, add support to configure them selectively.
While at it, fix the variable name used in read/write APIs to
reflect the address rather than base. Also use the pmic subtype
macros from qpnp-revid.h directly.
CRs-Fixed: 1071971
Change-Id: Ibbf3d432709eadf0808e062726804be6b2a065ee
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add initial set of configuration for GPU mempools
to reserve page pools at init time of kgsl driver.
CRs-Fixed: 1064046
Change-Id: Ie6789e13be7316a0de43538b9e477920fa64c6bb
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
A CPU that is isolated needs to have its timers migrated off to
another CPU. If while migrating timers, there is a running
timer, acquiring the timer base lock after marking a CPU as
isolated will ensure that:
1) No more timers can be queued on to the isolated CPU, and
2) A running timer will finish execution on the to-be-isolated
CPU, and so will any just expired timers since they're all
taken off of the CPU's tvec1 in one go while the base lock
is held.
Therefore there is no apparent reason to wait for the expired
timers to finish execution, and isolation can proceed to migrate
non-expired timers even when the expired ones are running
concurrently.
While we're here, also add a delay to the wait-loop inside
migrate_hrtimer_list to allow for store-exclusive fairness
when run_hrtimer is attempting to grab the hrtimer base
lock.
Change-Id: Ib697476c93c60e3d213aaa8fff0a2bcc2985bfce
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
If the new governor fails to start, switch back to old governor so that the
devfreq state is not left in some weird limbo.
Change-Id: I7cf1e6ceb63d27ce08b2d17b97a9844d257464ce
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Lock out interrupts during issuing dummy request in timeout to prevent from
a potential deadlock happening.
Change-Id: I986d8c36c839a1dee23761465ad331ffc31dd6ac
CRs-Fixed: 1008319
Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Yasir Malik <ymalik@codeaurora.org>
Add more information to the debugfs kgsl/proc/<pid>/mem which
will allow memtrack to correctly assign allocated ion buffer
memory to a process. The additional columns show the number of
kgsl_mem_entries which have a usage of egl_image (or) egl_surface.
When attaching a dma_buf to kgsl, use the dma_buf_attachment's
(void*)priv to point back to the kgsl_mem_entry. This makes it
possible to iterate through all attachments on a dma_buf and
gather statistics from each kgsl_mem_entry associated with the
dma_buf.
CRs-Fixed: 1073673
Change-Id: I1ef3bd0da3f74fa41074021699b2226c48bde9c3
Signed-off-by: Santhosh Punugu <spunug@codeaurora.org>
Convert most of the pmfalcon stub-regulator devices to a
rpm-smd-regulator devices. This ensures that requests made for
these regulators are aggregated by the RPM processor along with
the requests from other processors.
Also, add a dummy gfx_vreg_corner regulator until the CPR node
is added.
While at it, rename all regulators names and add pm/pm2 prefix
to differentiate between regulators on multiple supported PMICs.
Also update all clients with new regulator phandles.
CRs-Fixed: 1077493
Change-Id: I95b17de5bf17b62096d2c9d60633b6b30768752a
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Since usleep_range provides better accuracy in
comparison to msleep. This helps in reducing the
latency of host bus resume.
Change-Id: Id22104b9e5b63153731df9eb55759de9a86128c6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
A540v1 and v2 both need to enable the LMLOADKILL quirk for the
GPU.
CRs-Fixed: 1036444
Change-Id: I84243578a1ef2f9948f0c9a8c1c00dc6a31eb579
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL
and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers.
This is done to avoid a VPC corner case with local memory(LM)
which leads to corrupt internal state on A540 and its derivatives.
CRs-Fixed: 1036444
Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Embedded tputs depend on WAN RX desc size, but, every target
has its own limitations of memory and embedded tputs goals.
So, add parameter to configure WAN RX desc size through device tree.
Change-Id: I28c550058dd990c9c8cd368a2677097c7f057ccd
CRs-Fixed: 1081543
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Based on the hardware documentation, update the IMA error
handling and clear sequence. In addition, check for DMA errors
and clear it before SRAM transactions begin. Also, check for IMA
hardware status to run the IMA clear sequence during ima_init and
not just based on IMA exception status alone. This is to help
with FG SRAM access to resume again properly in case of an error
encountered.
Change-Id: I583fa51599a1cbbd029cb45c075429730d2e071b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
