This is a snapshot from msm-3.18 upto the
commit 262b8c5814ec ("edac: cortex_arm64_edac:
modify sbe detection to use perf events") for the
arm64 cache cpu erp bindings.
Change-Id: I7313a121440bf5a455401cf73bd5ef4d6c1506cb
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
This commit provides a mechanism for the host drivers to advertise the
support for different beacon intervals among the respective interface
combinations in a group, through NL80211_IFACE_COMB_BI_MIN_GCD (u32).
This value will be compared against GCD of all beaconing interfaces of
matching combinations.
If the driver doesn't advertise this value, the old behaviour where
all beacon intervals must be identical is retained.
If it is specified, then any beacon interval for an interface in the
interface combination as well as the GCD of all active beacon intervals
in the combination must be greater or equal to this value.
Signed-off-by: Purushottam Kushwaha <pkushwah@qti.qualcomm.com>
[change commit message, some variable names, small other things]
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
Git-commit: 0c317a02ca982ca093e71bf07cb562265ba40032
CRs-fixed: 1025311
Change-Id: Ie432af1fefc79f88ec67d212f8b9880355c4266d
Signed-off-by: Purushottam Kushwaha <pkushwah@codeaurora.org>
[pkushwah@codeaurora.org: This commit also includes fix for memory leak
which was introduced by 0c317a02ca982ca093e71bf07cb562265ba40032
320c975f180b19296f0fd6c5bf2144e633aaba5e:
cfg80211: fix possible memory leak in cfg80211_iter_combinations()]
Add node for QBT1000 (fingerprint sensor) which defines the
clocks which are used by the driver and GPIOs which are used
to signal IPC messaging and finger detection.
Add pmcobalt entry for MTP for physical home-button GPIO.
Change-Id: I3eb92f83b42b0fa28dc73f6e0d4f74ef50375855
Signed-off-by: Lior Barenboim <liorb@codeaurora.org>
Currently strobe control is cleared even when HW strobe control is not
explicitly enabled. Fix it.
CRs-Fixed: 1077179
Change-Id: I5bc6a5a46311206818d70567e31fd84adc0128be
Signed-off-by: ansharma <ansharma@codeaurora.org>
Initial support for all BLSP SPIs with default configuration
and disabled state such that clients can overwrite and enable
respective SPI instance as per need.
Change-Id: Ia60fc3ecb5c2aba19effe1c8242f2d89fdef3ebd
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Controller driver explicitly puts the controller in low power mode
when cable disconnected. However, due to config-fs and ADB design
which unbinds composition on every cable disconnect results in
detaching/stopping gadget driver on every cable disconnect. Gadget
stop will explicitly brings the controller out of low power mode to
disable events and ep0 which is not necessary as controller is
already in low power mode. These operations are not required for
composition switch as well because gadget pull-up call back will
take care of that. Hence, Remove disabling events and ep0 from stop
gadget callback.
Change-Id: If2b3e241076a4e0eeb87eeb4361398313fca6962
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Initialize mbhc pointer before it gets accessed from
a different thread.
Change-Id: Ie1a5038458b0b93dfec3e5bfc350686eb1f8eb1b
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Add support for printing the voltage voting info to the
clock_state ftrace events.
CRs-Fixed: 1082843
Change-Id: I6ab3992958a659995b7d5020287fd6e47e28f2a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
There is a posibility of a buffer overflow in scm_call,
add check to avoid the same.
Change-Id: Iee908c56ec530569b35dafa060139e0428efc781
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.
Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
On ARM systems the cache topology cannot be probed at runtime, in
particular, it is impossible to probe which CPUs share a given cache
level. Power management software requires this knowledge to implement
optimized power down sequences, hence this patch adds a document that
defines the DT cache bindings for ARM systems. The bindings are compliant
with ePAPR (PowerPC bindings), even though most of the cache nodes
properties requirements are overriden, because caches geometry for
architected caches is probeable on ARM systems. This patch also adds
properties that are specific to ARM architected caches to the existing ones
defined in the ePAPR v1.1, as bindings extensions.
Change-Id: I37ca3aae0471fcd60499615df77093d5b5451bf8
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
For hyp_assign calls, dest_vm_and_perm_info wrongly
defines ctx as u32 * type, while TZ expects it as u64.
This creates an inconsistency on 32bit system. Fix it.
Change-Id: I31e8e0b5e9ae240ca031f625cf7c49f1bfe165d4
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
The global mutex of 'gdp_mutex' is used to serialize creating/querying
glue dir and its cleanup. Turns out it isn't a perfect way because
part(kobj_kset_leave()) of the actual cleanup action() is done inside
the release handler of the glue dir kobject. That means gdp_mutex has
to be held before releasing the last reference count of the glue dir
kobject.
This patch moves glue dir's cleanup after kobject_del() in device_del()
for avoiding the race.
Change-Id: I92b10e62be8129ead5859a285bf964ab0a3ae2fd
Cc: Yijing Wang <wangyijing@huawei.com>
Reported-by: Chandra Sekhar Lingutla <clingutla@codeaurora.org>
Signed-off-by: Ming Lei <ming.lei@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-commit: cebf8fd16900fdfd58c0028617944f808f97fe50
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
If "core" memory resource is not specified, the driver could end up
dereferencing a null pointer.
Fix this by returning -EINVAL when core resource is missing.
Change-Id: Id08f7b2e109b6b2963b19dfe07f07cbfb424202b
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
