For LABIBB peripherals in pmicobalt, bootloader configures
LCD/AMOLED mode and SWIRE control based on a GPIO selector.
Hence, add support to configure them selectively.
While at it, fix the variable name used in read/write APIs to
reflect the address rather than base. Also use the pmic subtype
macros from qpnp-revid.h directly.
CRs-Fixed: 1071971
Change-Id: Ibbf3d432709eadf0808e062726804be6b2a065ee
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add initial set of configuration for GPU mempools
to reserve page pools at init time of kgsl driver.
CRs-Fixed: 1064046
Change-Id: Ie6789e13be7316a0de43538b9e477920fa64c6bb
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Update tasha DAI for 24bit record support.
CRs-Fixed: 1084375
Change-Id: I6d04b6343713a91d97ff18631141772f92f4ed00
Signed-off-by: Dhanalakshmi Siddani <dsiddani@codeaurora.org>
A CPU that is isolated needs to have its timers migrated off to
another CPU. If while migrating timers, there is a running
timer, acquiring the timer base lock after marking a CPU as
isolated will ensure that:
1) No more timers can be queued on to the isolated CPU, and
2) A running timer will finish execution on the to-be-isolated
CPU, and so will any just expired timers since they're all
taken off of the CPU's tvec1 in one go while the base lock
is held.
Therefore there is no apparent reason to wait for the expired
timers to finish execution, and isolation can proceed to migrate
non-expired timers even when the expired ones are running
concurrently.
While we're here, also add a delay to the wait-loop inside
migrate_hrtimer_list to allow for store-exclusive fairness
when run_hrtimer is attempting to grab the hrtimer base
lock.
Change-Id: Ib697476c93c60e3d213aaa8fff0a2bcc2985bfce
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Modify the code-dev mapping table for memlat to
further improve power and performance on msmcobalt v2.
Change-Id: Ida2c99d7fd56b5b277653c42808f08f4f23ed790
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
If the new governor fails to start, switch back to old governor so that the
devfreq state is not left in some weird limbo.
Change-Id: I7cf1e6ceb63d27ce08b2d17b97a9844d257464ce
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Lock out interrupts during issuing dummy request in timeout to prevent from
a potential deadlock happening.
Change-Id: I986d8c36c839a1dee23761465ad331ffc31dd6ac
CRs-Fixed: 1008319
Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Yasir Malik <ymalik@codeaurora.org>
Fd is tunneled using userptr memory type to v4l2 rotator
driver. Fd can assume the same value between multiple qbuf but
with the underlying mapping modified. However, v4l2 assumes that
if userptr of the same value are passed in, the underlying buffer
is the same and will bypass memory mapping callback. This will
cause problem for fd tunneling because the obsolete mapping is
used.
To ensure buffer mapping, add buf_finish callback to clear last
fd value before dequeuing buffer back to user client. This will
force the next queue buffer command to invoke memory mapping callback
since the incoming fd value is different from the reset value.
CRs-Fixed: 1084634
Change-Id: I932a58fc633918b151959fcbe320668a87dbc49c
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Add more information to the debugfs kgsl/proc/<pid>/mem which
will allow memtrack to correctly assign allocated ion buffer
memory to a process. The additional columns show the number of
kgsl_mem_entries which have a usage of egl_image (or) egl_surface.
When attaching a dma_buf to kgsl, use the dma_buf_attachment's
(void*)priv to point back to the kgsl_mem_entry. This makes it
possible to iterate through all attachments on a dma_buf and
gather statistics from each kgsl_mem_entry associated with the
dma_buf.
CRs-Fixed: 1073673
Change-Id: I1ef3bd0da3f74fa41074021699b2226c48bde9c3
Signed-off-by: Santhosh Punugu <spunug@codeaurora.org>
Any driver can use gpio as function, so adding all the gpios
to pingroups.
Change-Id: I4949954c7b546030a4a94c74bb68c2eb4f6d4718
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Convert most of the pmfalcon stub-regulator devices to a
rpm-smd-regulator devices. This ensures that requests made for
these regulators are aggregated by the RPM processor along with
the requests from other processors.
Also, add a dummy gfx_vreg_corner regulator until the CPR node
is added.
While at it, rename all regulators names and add pm/pm2 prefix
to differentiate between regulators on multiple supported PMICs.
Also update all clients with new regulator phandles.
CRs-Fixed: 1077493
Change-Id: I95b17de5bf17b62096d2c9d60633b6b30768752a
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
If a protocol converter or HUB or a dongle supports multi-function
to support both displayport and USB simultaneously and exposes
pin assignment D as supported one, prefer pin assignment D to be
configured on the ports.
Change-Id: Ia69987c0e15ec5f15a07ca3a0e44174ab6e5feb9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
The current generated link rate in software doesn't
consider fractional values. As a result, for few of
the boundary cases, the calculated link rate is not
correct. Fix this by checking for any fractional values.
Change-Id: I3366b70c7e5bfa2a240aa24f1e0c70b54d686721
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the FRAC_START3 register settings for 5.4 GHz link
rate in Display-Port PLL driver. This is needed for accurate
link and pixel clock values.
Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the MISC settings register according the color
depth and format. Update the MVID and NVID registers
using the M and N values used to configuring
the DP pixel clock.
Change-Id: I67e08d3491fbb7c0960c463cc8f979238b89d818
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Since usleep_range provides better accuracy in
comparison to msleep. This helps in reducing the
latency of host bus resume.
Change-Id: Id22104b9e5b63153731df9eb55759de9a86128c6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
A540v1 and v2 both need to enable the LMLOADKILL quirk for the
GPU.
CRs-Fixed: 1036444
Change-Id: I84243578a1ef2f9948f0c9a8c1c00dc6a31eb579
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL
and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers.
This is done to avoid a VPC corner case with local memory(LM)
which leads to corrupt internal state on A540 and its derivatives.
CRs-Fixed: 1036444
Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Embedded tputs depend on WAN RX desc size, but, every target
has its own limitations of memory and embedded tputs goals.
So, add parameter to configure WAN RX desc size through device tree.
Change-Id: I28c550058dd990c9c8cd368a2677097c7f057ccd
CRs-Fixed: 1081543
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Based on the hardware documentation, update the IMA error
handling and clear sequence. In addition, check for DMA errors
and clear it before SRAM transactions begin. Also, check for IMA
hardware status to run the IMA clear sequence during ima_init and
not just based on IMA exception status alone. This is to help
with FG SRAM access to resume again properly in case of an error
encountered.
Change-Id: I583fa51599a1cbbd029cb45c075429730d2e071b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
When running concurrent video session, there are some possibilities
that CPU may take more than a second to schedule hfi work handler.
In those cases, one of the threads which is waiting for the response
is timing-out.
Increase hw response timeout and power collapse timeout will give
more time for hfi work handler to be scheduled and process the response
messages.
CRs-Fixed: 1086284
Change-Id: I768ef6c941c791af5a45d846fa81d810b831efa5
Signed-off-by: Karthikeyan Periasamy <kperiasa@codeaurora.org>
