The select_best_cpu() algorithm selects the previous CPU as the target
CPU if the task did not sleep for more than 2 msec (controlled by
/proc/sys/kernel/sched_select_prev_cpu_us). The complete CPU search is
not done for a long time for tasks which sleeps for a short duration
in between the long execution slices. Enforce a 100 msec threshold since
the last selection time to run the complete algorithm.
CRs-Fixed: 984463
Change-Id: I329eecc6bae8f130cd5598f6cee8ca5a01391cca
[joonwoop@codeaurora.org: fixed conflict in bias_to_prev_cpu() and sched.h
where CONFIG_SCHED_QHMP used to be.]
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Add support to map/unmap TMC flush and reset CTIs as part of TMC
enable/disable.
Change-Id: I5aae2ce3d2e0dec252139db571d4598d49f3a371
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
ETM driver sets the address comparator in TRCACVR0 and TRCACVR1.
Enable default inclusive range selected by these registers.
Change-Id: I08d798d6fb24571856929f84db572bbd3651cd6c
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Change to make sure that CTIs get probed before CoreSight sources and
sinks.
Change-Id: I7e83fe663c32a6d75470bb0cb546b42c9fe04ab1
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to read cti data from OF nodes.
Devices can use this data to configure CTIs as part of their
configurations.
Change-Id: I55b0534ab4d81b9ce02378b513e6ae9bc3b6cd1e
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
bio's without data are not relevant, bio_had_data checks this,
replaced redundant checks to call to this function.
Also, additional clean ups performed
Change-Id: I315bcf43cf3d32e78d53b818571da1f5175f8ac3
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
Implement a new ioctl that sets the ahb clock vote. This can be
used from user space to make register programming quicker.
CRs-Fixed: 1001335
Change-Id: I1bc0253ada50040d55b57f0ed07ba66b5535106a
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Interfaces like MBIM or ECM is having multiple data interfaces.
In this case, SET_CONFIG() happens before set_alt with data interface 1.
Due to this, TXFIFO of GSI IN endpoint is not resized causing low
throughput in DL direction. Fix this issue by using mult as 3 for
GSI related USB IN endpoint irrespective of super-speed or high-speed
mode.
CRs-Fixed: 1025031
Change-Id: I10de98ae57284699af3abcd90bafac63ba03844e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
IPC Router assigns NULL to write_space callback for all sockets in its
family by defaults. The setsockopt operation with SO_SNDBUF option
accesses write_space callback without checking its validity. This may
lead to a NULL pointer dereferencing when that operation is performed.
Assign a dummy write_space callback operation by default to all IPC Router
sockets.
CRs-Fixed: 1025150
Change-Id: Id2454683116c948b7bb4fa3c50a91a5a9585a491
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Sending PP params and calibration params for compress
passthrough path is resulting in timeout which is
delaying the start of playback.
Sending the PP params only when it is legacy pcm playback.
Change-Id: I7fe2840b7a72bddde887340a6e913cb120d1bc61
CRs-Fixed: 1030688
Signed-off-by: Satish Babu Patakokila <sbpata@codeaurora.org>
commit 19bacdc925 ("usb: dwc3: core: only setting the
dma_mask when needed") does not allow to modify dma mask if it
is already set. Since the platform device has default 32-bit
dma mask set change prevents to update the dma mask to 64-bit.
This leads to kernel panic due to out of SW-IOMMU space when a
function driver tries to map more than 32-bit wide address.
Change-Id: I38b178f38277f9a2fa40735f4e15385638403ae6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
We are seeing the kernel panic due to NULL pointer dereference with
following call trace:
sdhci_msm_set_clock+0x59c/0xa28
sdhci_do_set_ios+0xf4/0x740
sdhci_set_ios+0x28/0x3c
mmc_set_ios+0xac/0x1ec
__mmc_set_clock+0x2c/0x3c
mmc_ungate_clock+0x20/0x28
mmc_host_clk_hold+0x54/0xc4
mmc_power_off+0x1c/0x70
mmc_rescan+0x250/0x27c
process_one_work+0x240/0x420
worker_thread+0x268/0x390
kthread+0xf8/0x100
This is happending when eMMC initialization is failing in HS400 mode.
sdhci_msm_set_clock() might be accessing the card pointer after it
was deallocated, this change adds the safety checks to avoid NULL
dereference.
Change-Id: I895b8b33cce4173100d58acf690e57b5f4e69081
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
RTB logs gets flooded during console write operation due to logged
variant of API. This commit replaces logged variant API with no log
variant to suppress logs.
CRs-Fixed: 1030352
Change-Id: I79f943cbc13553b3dbdce68f5c1143fa54f6eafa
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
The cycle counters are read often by the scheduler to perform
CPU clock frequency estimation. Remove logging the counter reads
to prevent unnecessary logging to the RTBs.
Change-Id: I15e26e4d46d5ee663923d5678fa75878636e6940
CRs-Fixed: 1023437
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Allow virtual timers i.e. CNTV_TVAL_EL0 to be accessed
by userspace.
CRs-Fixed: 1018301
Change-Id: I724ddbf4e7c02ee25622c6712210aee948d037f6
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Change the memory the zap shader is allocated from the
peripheral_mem region to the default CMA pool for msmcobalt.
Change-Id: I6ea31b8a17107b9f42c82a7b05919ee8ed798474
Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
The alloc_flags argument of zone_watermark_ok_safe()
is no more available. Fix the usage.
Change-Id: I99b832418b914765a4941682929dd7183d274e1c
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add a cold_boot parameter which supplements the
boot_reason sysctl entry with information about
whether the system was booted from cold or warm state.
/proc/sys/kernel/cold_boot entry is updated with 1 or 0 when
system was booted from cold or warm boot state respecitively.
CRs-Fixed: 461256
Change-Id: I2bc5d80c8f26eb9e9dbb4b34960d991a51a224e4
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
[abhimany: fixup minor merge conflict and drop changes to
kernel/sysctl.c and Documentation since it was brought in via
snapshot commit]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
During board initialization read the shared memory item
SMEM_POWER_ON_STATUS_INFO and place it in the procfs at
/proc/sys/kernel/boot_reason
The data item is an integer with a bit being set to identify the reason
the device was powered on. The values of this data item is defined in
the document Document/arm/msm/boot.txt, the following is the data in the
documentation file.
power_on_status values set by the PMIC for power on event:
----------------------------------------------------------
0x01 -- keyboard power on
0x02 -- RTC alarm
0x04 -- cable power on
0x08 -- SMPL
0x10 -- Watch Dog timeout
0x20 -- USB charger
0x40 -- Wall charger
0xFF -- error reading power_on_status value
This is cherrypicked from commit <372d39f87b0da75>
("put reason for boot in procfs") of 3.18 tree.
Change-Id: I59e665f92e6e29f7dfef4380314f676a2d92c94b
Signed-off-by: Rick Adams <rgadams@codeaurora.org>
[abhimany: fix up minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
add support for using 64bit dma mask on ipa3 to
resolve the dma pool exhausted issue.
Change-Id: I887d10efa520eb61d814f4f5d0f8e32916f38450
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
add 64bit dma mask support on ipa3 to resolve
the dma pool exhausted issue.
Change-Id: I629e2ae15574ab779c43dd40d40cf169fe19bb8e
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Add implementation of spcom_is_sp_subsystem_link_up() kernel API.
Remove Load App API declaration,
as it is not supported for kernel drivers.
Change-Id: I76a43a04d454d1f25a640831f43b51dbb7e75943
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
The format specifier %p can leak kernel addresses
while not valuing the kptr_restrict system settings.
Use %pK instead of %p, which also evaluates whether
kptr_restrict is set.
Change-Id: Ib1adf14e9620ad7b1bd3e962001c852610210d46
Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
Currently ASoC core creates a static route b/w
playback/capture widgets of cpu and codec dai
if they are part of the same dai-link. However
this will cause codec path to get powered up first
followed by the backend dai start during device
switch use-case where the front-end is not closed,
leading to audio playback failure if either bit-width
or sample rate is different.
CRs-Fixed: 1029118
Change-Id: I180515f2ad55d1f446ad7eb1ad0bd71809db94bd
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
When some data is written to a file both mmap and regular io
there can be race conditions that can cause incorrect data
to be saved.
Disable passthrough on the specific files on which mmap is called
until we add mmap support to passthrough.
Change-Id: Ic24219ab22d3130aa7e9e998a9e6798648a7321c
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
IPA Filtering and Routing rules and tables building is
a logic related to IPA H/W. As such, migrating this
logic to IPAHAL (H/W abstraction layer) of IPA driver
and adapt the core driver code to use it.
New internal S/W API is added to access IPAHAL for
Filtering and Routing rules and tables building and
clearing.
CRs-Fixed: 1006485
Change-Id: I23a95be86412987f72287138817235d3f1f9bc61
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
The max_possible_efficiency and CPU's efficiency are fixed values which
are determined at cluster allocation time. Avoid division on the fast
by using precomputed scale factor.
Also update_cpu_busy_time() doesn't need to know how many full windows
have elapsed. Thus replace unneeded division with simple comparison.
Change-Id: I2be1aad3fb9b895e4f0917d05bd8eade985bbccf
Suggested-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Updating cycle counter should be serialized by holding rq lock.
Add missing rq lock hold when cycle counter is updated by irq entry
point.
Change-Id: I92cf75d047a45ebf15a6ddeeecf8fc3823f96e5d
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Task execution time in nanoseconds and CPU cycle counters are large
enough to cause overflow when we multiply both. Avoid overflow by
calculating frequency separately.
Change-Id: I076d9ecd27cb1c1f11578f009ebe1a19c1619454
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
The function parameter cpu isn't used anymore by cpu_cycles_to_freq().
So remove it.
Change-Id: Ide19321206dacb88fedca97e1b689d740f872866
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Increase the char buffer size for the sync fence name from
32 to 64. This makes it possible for drivers to use a longer,
more descriptive name for sync_fence, which improves the
readability of the sync dump in debugfs.
Change-Id: I8a54ec1c7b95764fe3a39f00ce392fddcfd261f1
Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
Define the open-loop and closed-loop fused corner voltage
margin adjustments for CPR local rev >= 1 parts. This ensures
the CPU clusters powered by VDD_APC0 and VDD_APC1 rails on
CPR rev >= 1 msmcobalt chips have sufficient voltage margin
for stable operation.
CRs-Fixed: 1030441
Change-Id: I3d9cf9179c78619933c11d966ae19a8851749595
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Enabling the configuration for qtaguid which is needed for
enabling bandwidth control from userspace.
Change-Id: I5d0fe18bbef5b80085a9cd77f49eb77e3c654542
CRs-Fixed: 1030408
Signed-off-by: Bryse Flowers <bflowers@codeaurora.org>
Changes to support MIPI Cphy mode on CSID version 5.0.
CRs-Fixed: 1030317
Change-Id: I6e0835811a47820714eddcf851ea15ece729c2bb
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Add support for the mdss_mdp_lut_clk clock on MSMCOBALT.
In addition, remove toggling the memory retention bits for the
mdp core clock during gdsc_enable/disable. The display driver
will use the set_flags API to set the core clock memory retention.
CRs-Fixed: 1025605
Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Starting with DSI PHY hardware revisions 3.0 and above, data lane swap
configurations need to be programmed via the DSI PHY interface. In other
cases, a new register interface has been introduced to program the lane
swap configuration for DSI controller revision 2.0 and above. Refactor
the existing implementation to account for these hardware changes.
Change-Id: I3772c614bfee0ed13f30a38535bb814158d23226
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add code to allocate memory for dumping TMC register and buffer data.
These memory locations can be used to store TMC registers and buffer
information after a crash.
Change-Id: I8e98178110efa8e455a329e358c471757e87f2d1
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
DSB_TIER.PATT_TYPE bit can be used to choose a driver for
pattern matching based timestamps for DSB subunit.
Add support to configure this bit.
Change-Id: Id07ee18006c96e9a66cab5f4e7544dda85a692f8
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
The IBB pulse-skip and NLIMIT DAC configuration should be disabled
before applying the 2nd SWIRE command skip logic, to guarantee
that the IBB voltage changes immediately in the subsequent
SWIRE command. After the WA is completed, the pulse-skip can
be re-enabled after a programmable delay. Add this logic and
a DT property 'qcom,swire-ibb-ps-enable-delay' to configure
this delay. If this delay is not specified in the DT it defaults
to 200ms.
CRs-Fixed: 1010085
Change-Id: Ifec458a0028c16440ffd6ac1f6fa58eebc815c5a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Change-Id: Icaa1b68652eb4c836e8aacad80ff6cebe34cad4f
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Change-Id: Ic720d45d8c78e6c5a901e58ec6fd23fa15302a21
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Change-Id: I53cb4364e84d108f4fc211ca5524ca25d569997c
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Change-Id: If8a3e492e1c227cbf42f4f9907cdcb0dcb3ccc11
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
We can't control eSE power through driver as of now
so adding gpio pin support for eSE in NQxxx driver.
Multiline comments are updated.
Change-Id: I60651052d7bf97a8a0505e76904cebe2b7c69ce2
Signed-off-by: Gaurav Singhal <gsinghal@codeaurora.org>
In the current implementation N_MULTIPLIER bit for audio packets
on HDMI TX controller is not getting set properly. Fix this issue
by setting the multiplier value according to the sample rate set
for audio playback.
Change-Id: I25ab63eeadd5fd08649e9e828dcab83ec1b60161
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Rename wcd-gpio-ctrl to msm-cdc-pinctrl as these
changes are not wcd specific.
CRs-fixed: 1028800
Change-Id: Iffc36dd27ae3b651b736acab004d6fff3bdcb2c7
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
