DCC (Data Capture and Compare) is a DMA engine which is used to save
configuration data or system memory contents during catastrophic failure
or SW trigger.
It can also perform CRC over the same configuration or memory space.
Change-Id: Ic8a804250ab8b7ac501bd186d2e6f7506bb9b21a
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add the necessary frequency configuration to the OSM and CPUfreq
device nodes to allow frequency scaling of the Silver cluster in
msmcobalt to SVS Fmax.
Change-Id: I8153e1c2ad9cb320a4c116593b15898dbe2f6ca2
CRs-Fixed: 1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Raise the VDD_APC0 and VDD_APC1 CPR floor voltages to be equal to
the Nominal ceiling voltage on CPR revision 0 parts. Also, increase
the number of supported fuse combos to 8, to support up to 8 CPR
revisions using a single speed bin. This ensures stable operation
on some msmcobalt CPR revision 0 parts that cannot operate
reliably with SVS2/SVS voltages and has no impact to CPR rev 1 and
greater parts.
Change-Id: I6913a168596b34f527f689360f93fdf15b7d2f10
CRs-Fixed: 1014782
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The pipe format enumeration is not accounting for multi-rect on the
pipe list. Update the loop enumerating formats to account for multiple
rectangles per pipe.
Change-Id: Ief1980e2888525434e876f7cec4357403ca20cb1
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Fix macro name so CONFIG_SCHED_HMP_CSTATE_AWARE=y to take effect.
Change-Id: I0218b36b2d74974f50a173a0ac3bc59156c57624
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Tsens controller wont be able to send any temperature data in RUMI.
This will block LMH driver in HLOS during profile switch.
Disable LMH driver probe for RUMI to avoid this profile switch and
lock up.
CRs-Fixed: 1015361
Change-Id: Id54c09e0cf2c3701c10c71d6688417d3f5d4c08e
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
This reverts commit 28f67e5a50 ("sched: set HMP scheduler's
default initial task load to 100%") since 100% of init task load
makes too much of power inefficiency on some targets.
CRs-fixed: 1006303
Change-Id: I81b4ba8fdc2e2fe1b40f18904964098fa558989b
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux)
which allows the pixel clock to be either sourced out of the VCO clock
or the bitclock. In the current code, the ops for this mux clock is
overloaded incorrectly which results in the pixel clock being always
sourced out of the bit clock. Fix this by using the default mux clock
ops for this clock.
Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In glink_core_channel_cleaup there is a race condition while
traversing the channels list. This change holds the xprt
channel spinlock during the list manipulation.
CRs-Fixed: 988266
Change-Id: Idcff59ca1483fd98173255d6258e6771d91dec19
Signed-off-by: Chris Lew <clew@codeaurora.org>
This reverts commit 7b1a1d2263 ("defconfig: enable msm serial console
on msmcortex perf config").
We do not need this change since USB issue is fixed. No longer need
console to connect or disconnect USB.
CRs-Fixed: 1015006
Change-Id: I49154af38f0c59f6add8a38ebbc06f7dcfc85373
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Enumeration for writeback is not properly done because not all
information from device tree has been retrieved before setting up
supported formats. Moved this call until all data has been retrieved
from device tree and hw pre initialization.
Change-Id: Id228bf7ec564669fa8e9e739e27052de0133cc4d
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Data Capture and Compare (DCC) is a DMA engine, to capture or to
perform CRC over configuration data or system memory.
Add ids for DCC registers and sram data.
Change-Id: If76ef1325b1be623626742b0f0172a1675f21d63
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Fix the memory leak in common_log_register_log_buf() function
when registering log_first_idx with the memory with dump v2 driver.
Also use kmemleak_not_leak when msm_dump_data_register() calls
are successful to ensure that kmemleak doesn't report it as a memory
leak.
CRs-Fixed: 832905
Change-Id: I36eaeebf821f64dd7503ec823aca3c7aec846bd0
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Allocate memory to dump RPM CODE RAM at the time of crash.
Change-Id: I5062d65a095538a508944315e6cc06f430382bf5
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Allocate memory to dump VSENSE registers at the time of crash.
Change-Id: Ibd896873bc40b723071c66ca7cf1a4bc9b38ad5e
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Register for dumping 4KB of memory to dump PMIC
registers which can be parsed in case of device crash.
Change-Id: Idbf26d6241ab9a87e4dcea42723428289f2a869d
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
This snapshot is taken as of msm-3.10 commit:
78c36fa0ef (Merge "msm: mdss: Prevent backlight update during
continuous splash")
Common log registers the kernel log buffer address with the
memory dump driver so that the __log_buf can be collected from
ramdumps without the need of an external System.map file.
Change-Id: Ibeb74ca064e78fe7522e46b3c32bb362082d5d24
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Create and add PCIe resources such as register bases, clocks,
regulators, GPIOs, etc. to msmcobalt devicetree and pinctrl
devicetree.
Change-Id: I7a41ed6dd0f78cba140a15661d44b2f6c2745e39
Signed-off-by: Tony Truong <truong@codeaurora.org>
Enable MSM PCIe bus driver in defconfig for msmcobalt.
Change-Id: I44ece35ed1d8dda4d8139dfb54adc7a2e9c49383
Signed-off-by: Tony Truong <truong@codeaurora.org>
Some msmcobalt PCIe configuration registers have different
offsets than other chipsets. Update these offsets so
that PCIe can be correctly configured on msmcobalt.
Change-Id: I42c7f545a48e6a431ccdba062399776e8c1c64f2
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add device and vendor ID for PCIe on msmcobalt based on PCIe
core's configurations. This value is required to enable
PCIe low power management features.
Change-Id: I972c35c79327e3baa38573318ed0909d4daa9516
Signed-off-by: Tony Truong <truong@codeaurora.org>
SMMU SIDs allocated for PCIe varies across chipsets.
Thus, add support to retrieve the base SID from
PCIe devicetree node so that PCIe bus driver can
use it to calculate and assign to each PCI device.
Change-Id: I7651f2cbc53587f5b48501855260c87af2a2db01
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe PHY on msmcobalt has different register offsets and does not
support the same PHY sequences as other platforms. Thus, update
the PHY register offsets and sequences for msmcobalt.
Change-Id: If87bd507228476fee9713f88c06a1cf04b13f163
Signed-off-by: Tony Truong <truong@codeaurora.org>
Rather than using debugfs, switch to tracefs which trace
moved to in kernel 4.4.
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: I52ef7d45cabb20cc61fbd2fb3ef5016b041bc56c
PCIe PHY varies between each chipset. Thus, the PHY init sequence on
each of these chipsets are also different. Therefore, add the support
to read PCIe PHY init sequence from devicetree.
Change-Id: I21c2ce2b7d3bf1541a5d3580db4bc40497701095
Signed-off-by: Tony Truong <truong@codeaurora.org>
Although rotator driver checks for hardware version, and rejects
unsupported version. But it does not return error code to indicate
error condition, and causes driver crash.
This fix adds error code to unsupported version, so upper layer can
properly handling the condition.
CRs-Fixed: 1015335
Change-Id: If83199b5990a3623b1018058d2164862352902b7
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Disable the OSM vred FSM until core-count adjustments are enabled
for the CPRh VDD_APC0 and VDD_APC1 devices.
Change-Id: I467f49edbc65449f29f761c6b873ca702d24fa72
CRs-Fixed: 1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add additional required clocks to mdss device tree to enable
mmss smmu and ahb access for rotator.
CRs-Fixed: 1008505
Change-Id: I5bfc16e3d6ac3c6052b8dca55b42b57480ec650e
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Fixes 2 problems related to multi-kernel tree support:
1. Copying of modules to /system/lib/modules is broken when building
in a multi-kernel tree. This is because INSTALL_MOD_PATH is not
set correctly. When building a multi-kernel tree, the output
directory is one additional directory deep, so modules end up
under <out>/obj/system/lib/modules instead of
<out>/system/lib/modules. Fix this by using BUILD_ROOT_LOC
which is set appropriately for multi-kernel and standard trees.
2. When running "make kernelconfig" on a multi-kernel tree,
the generated defconfig is copied to the wrong location,
since it uses the old-style location under kernel, instead
of kernel/<kernel name>.
Change-Id: I90563104a5b6219472eaeae1964fc34b52586536
CRs-Fixed: 1014872
Signed-off-by: Lior David <liord@codeaurora.org>
Some MSMCOBALT parts with CPR revision 0 are unable to operate at
low voltage. Therefore, raise the CPR floor voltage to be equal
to the Nominal ceiling voltage for all corners. Also increase
the ceiling voltages for corners accordingly to ensure that the
ceiling >= floor voltage requirement is met.
Change-Id: I346a909984519c2522503f842d449c6f3217b746
CRs-Fixed: 1014407
Signed-off-by: David Collins <collinsd@codeaurora.org>
Enable ssphy and update the qmp phy initialization sequence
to enumerate in super speed mode. By default Lane A is
selected for super speed mode.
Change-Id: Ibd5fdd0a1f48ecd8a828d187ac86513e3f48ae6f
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Add mmss_mnoc_ahb clock to mdss device tree as this clock needs to be
turned on before turning on ahb_clk.
CRs-Fixed: 1008505
Change-Id: I43ccff9774d098d551c4ba25ad5678fee13aca1f
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Add new USB rx and tx afe ports and routing to different
fe dais to enable USB audio via ADSP.
Change-Id: I4f82ba27becee1f3b62c410be0d00876961f9b18
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
The only dependency for irq time accounting is a sufficiently high
resolution timer. Plenty of arm64 platforms will have this, so enable
this feature.
CRs-Fixed: 1013947
Change-Id: Id675a541a6813a14ae0b7e1bb66670bf7467a97f
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
[satyap@codeaurora.org: trivial merge conflict resolution.]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Enable CPUSS dump driver to dump cpu subsystem during crash.
CRs-Fixed: 1011333
Change-Id: Id4a8bca3eb77db4f998c790f1927fe373684048a
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
This snapshot is taken as of msm-3.18 commit dacccc6.
CRs-Fixed: 1011333
Change-Id: I4ed06b5602220ed4e30bd37a0633ccb3454f7d43
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Use correct index value while accessing DCI channel status.
Change-Id: I97456326a40c6d24c208307a9e8e6a55fc5b9d59
Signed-off-by: Sreelakshmi Gownipalli <sgownipa@codeaurora.org>
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The pcie_aux_clk_src needs to run at XO frequency instead
of at 1MHz. Update the clock driver to support that.
CRs-Fixed: 1013278
Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the base address of GPIOs to the correct value.
CRs-Fixed: 1014950
Change-Id: Id232492bd458dac04e89a94ed5a85092223ebff6
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
This change separates the control and config register offset nodes
for ping pong blocks. Its not necessary every ping pong
blocks to have both control and config registers.
Change-Id: Ide998ad71abccb35d899f9e1f6093949acb95b09
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
With LMH DCVSh hardware, the current check will use cpufreq to
limit both scaling min and max frequency. But cpufreq should be
used only for scaling min frequency.
Update the check to use cpufreq only to limit scaling min frequency.
Change-Id: I38de1699a7cdd5bc3fecef80dd34c4d22d2fd200
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
With LMH DCVSh hardware, thermal driver can directly vote in the
hardware to limit the scaling max frequency. Voting to the cpufreq
driver along side the hardware, will introduce software delay when
removing the mitigation.
So avoid voting the scaling max frequency to the cpufreq when LMH DCVSh
is available.
Change-Id: I8a5f913ae41263b06af99b0ee802b4fa68312f33
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Enable bcl peripheral driver. The driver will interact
with the bcl peripheral to get the battery current, battery
voltage and set and receive thresholds for the same.
CRs-Fixed: 1010115
Change-Id: I7168c754e939ef9da001bcac52a5b802dea40b41
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Add slimbus_6_rx back-end dai-link for msmcobalt to enable
independent backend for different devices during audio playback.
Change-Id: If22cadbcfac92f8243a3b6d3201935a839cd701a
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Add device tree entries for USB audio rx and tx to
support USB audio via ADSP on msmcobalt platform.
Change-Id: I345aa2369d18e2137ce79676049bb59d715d1ee0
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
GSO segmented packets are getting linearized
before being sent to rmnet_ipa interface since SG
feature is not enabled.
Add NETIF_F_SG to IPA's HW features so that
ethtool can be used to enable it.
Change-Id: I7b321c796935febb3fa3e9ae520fd65e00da507c
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Camera sensor probe happens in camera daemon, because
of delayed start of camera daemon, timeout happens and
camera server is notified with 0 cameras, this is
temporary solution.
CRs-Fixed: 1014373
Change-Id: I957b9744f6f627a74f805933012429c41b910e92
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
