The current PHY sequence is not fully compatible with the
QSERDES PHY found on mdmcalifornium. Thus, add the new
sequence and other changes to support PCIe QSERDES PHY
on mdmcalifornium.
Change-Id: I5a5d0b115651a159612e17debf0d25d6f88dbee8
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe bus driver can now use devicetree to help distingush
which PCIe QMP PHY version is being used. This will allow
PCIe bus driver to choose the correct PCIe PHY sequence.
Change-Id: I74c67431b75292bb1db3e4b97d89d69de9b6f11b
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for 3.18 kernel. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Signed-off-by: Tony Truong <truong@codeaurora.org>
SMMU requires PCIe to provide a SID for each of its endpoint
so that the endpoint can successful transaction on the bus.
This change adds the support for PCIe bus driver to calculate
a SID for its endpoint and give it to the SMMU driver.
Change-Id: I52099bbfed0a38c75b0277b0f58f45f6e6559695
Signed-off-by: Tony Truong <truong@codeaurora.org>
Some EP requires additional GPIO to be enabled for link training.
Add the support in PCIe Bus Driver to manage this GPIO.
Change-Id: I837edae478779fdaf3e94c70a0a031f9d0580a77
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe on some targets require the iommus device tree entry.
Therefore, add this device tree entry to the PCIe
documentation.
Change-Id: Iec6c4cfcd5e51d6aa1259bb826fe60d131072170
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support PCIe MSI on 3.14 kernel, the client's host
driver must use the QGIC IRQ number to request/enable
the interrupt while the client's firmware must use
the SPI number to trigger the interrupt. Therefore,
add this logic in PCIe bus driver to support MSI
interrupts on 3.14 kernel.
Change-Id: I165022281c9e795be8c5e2e4a4faa34d4c004a45
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for thulium. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the clock power management for the
endpoint.
Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the common clock configuration for the
endpoint.
Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c
Signed-off-by: Tony Truong <truong@codeaurora.org>
This PCIe bus driver snapshot is taken as of msm-3.10 commit:
803998b (Merge "ASoC: wcd: don't set autozeroing for conga")
This change adds the PCIe bus driver and its dependecies from
msm-3.10 to msm-3.14. All the files are as is from msm-3.10.
No additional changes were made.
Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34
Signed-off-by: Tony Truong <truong@codeaurora.org>
This snapshot is taken as of msm-3.18 commit 95a59da3cf
(msm: hdcp: proper state sanitization for different versions)
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Add driver for core hang detection.
This drivers provides sysfs entries to configure
threshold, pmu event select and enable parameters
for core hang detection feature.
Change-Id: Ieb19b309238fc11f1a631842564a7e43b16651dc
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Add driver for gladiator hang detection.
This driver provides sysfs entries to configure thresholds,
enable parameters for ACE, IO, M1, M2, PCIO gladiator ports.
Change-Id: Ib4bfa084a4265d6b6a149e8c932a5e6f884a043e
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Add support for gladiator cache interconnect error
detection and reporting. The Gladiator is the cache
coherent interconnect in between two or more CPU
clusters. This driver helps detect the errors related to
snoop data transfer and Distributed Virtual Memory(DVM)
on READ/WRITE transactions.
Change-Id: Ic1aa2066df239672a8ed3d99a63318ed32a11af2
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add the MSM SPS (Smart Peripheral Switch) driver.
SPS may be used as a DMA engine to move data in either Peripheral-to-
Peripheral (a.k.a. BAM-to-BAM) mode or Peripheral-to-Memory (a.k.a
BAM-System) mode.
This snapshot is taken as of msm-3.18 commit 132e1315c1
Change-Id: I7ec9781c3b608b9ee0fffdf7ba3e1b33bfa4dfcd
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add TSENS Thermal driver. Include support to activate
a trip type and mode.
This snapshot is taken as of msm-3.14 commit 3bc54cf86b
(Merge "msm: camera: Add dummy sub module in sensor pipeline")
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Conflicts:
drivers/thermal/Kconfig
drivers/thermal/Makefile
include/linux/thermal.h
Change-Id: Ie8a089afc0cf9e45ac000dff425a3e6206c1b9b1
This is a snapshot of the MSM sharedmem driver as of msm-3.14
commit:
149717c082aab8168283b7e0c23d8bd5a45b1999
( uio: msm_sharedmem: Add custom mmap )
The following changes are included:
02d55287 uio: msm_sharedmem: Restrict debugfs write to root.
de961fc7 uio: msm_sharedmem: Return ENOMEM if the shared mem addr
is zero.
b974ce64 uio: msm_sharedmem: Add addtional information to debugfs
c46af547 uio: msm_sharedmem: Add support for dynamic shared memory
allocation
Change-Id: I49902f018bde1d59d41027b7e46268cc17231a3e
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
This is a snapshot of PIL, SSR and SYSMON drivers and libraries as
of msm-3.18 commit
5cef33a285e91869cebe40a25e6294ae1e5fc9cc
(Merge "ASoC: msm: Update the AFE clock API support")
Change-Id: Ibebddee32b15fbcb5b18cceac43769d3309e609c
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Add a DT property that decides whether to allow controller
low power mode upon bus suspend, which will be invoked by
the OTG state machine.
It is also required to take the core out of LPM in case
ep_queue is called by the upper layers. In this case,
remote wakeup sequence will be initiated once the core
is out of LPM.
[jackp@codeaurora.org: Squashed with dwc3 changes from
"usb: dwc3: Add new OTG state OTG_STATE_B_SUSPENDED"]
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Currently USB DWC3 controller's internal clock gating is disabled
unconditionally. In few platform, it is possible to enable internal
clock gating with controller. Hence this change adds support to
disable this functionality conditionally using "snps,disable-clk-gating"
device tree property. With this change USB controller's internal clock
gating is enabled by default.
CRs-Fixed: 851877
Change-Id: I17d43a23d3bff0cb516b952c35c4a13af53f7777
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Setting SSPHY SUSP bit (bit 17) in GUSB3PIPECTL(0) register
might cause device enumerating at high speed mode instead of
superspeed mode on some platforms. Hence add workaround by
clearing the SSPHY SUSP bit during disconnect and setting it
after it is configured to fix this enumeration issue on those
platforms.
Also add support for disabling U1 and U2 low power modes which
could also affect this enumeration issue.
CRs-Fixed: 637902
Change-Id: I8668ced09a88b77f37265ab15e89fa9e964bfbe9
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
[jackp@codeaurora.org: only add u1/u2 disable bits]
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add a device tree property to allow setting the GUSB3PIPECTRL
Elastic Buffer Mode (bit 0). By default set the buffer to
half-full to work around SuperSpeed link errors. If the property
is set, set the buffer to be nominally empty.
This change is a combination of two previous commits:
USB: dwc3: core: Set elastic buffer mode to zero
Currently elastic buffer mode in GUSB3PIPE_CTRL(0) register is
set to one. This results in high link error rates and superspeed
mode transfer failures if VDDCX is at super turbo mode voltage
1.05V. Hence set elastic buffer mode to zero in GUSB3PIP_CTRL
register.
usb: dwc3: Do not set half-full elastic buffer
On some platforms setting of half-full elastic buffer will cause data
corruption and hence we need to avoid this setting.
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Jack Pham <jackp@codeaurora.org>
This is a snapshot of phy-msm-{hsusb,ssusb,ssusb-qmp,qusb}.c
taken as of msm-3.18 commit 9da4ddc18727 (Merge "clk: msm:
clock-gcc: Associate gfx rail voting with gfx3d branch")
Also replaced ARCH_MSM dependency with ARCH_QCOM in the Kconfig.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add dwc3-msm.c and associated driver files. Note these are
based on the downstream implementation and will coexist
(for the time being) with dwc3-qcom glue driver until they
can eventually be merged.
This snapshot is taken as of msm-3.18 commit a3883c356869 (Merge "input:
touchscreen: correct condition checks in ITE tech touch driver")
Signed-off-by: Jack Pham <jackp@codeaurora.org>
For some use cases, it is not known beforehand, how much
removed (carve-out) region size must be reserved. Hence
the reserved region size might need to be adjusted to
support varying use cases. In such cases maintaining
different device tree configurations to support varying
carve-out region size is difficult.
Introduce an optional device tree property, to
reserved-memory, "no-map-fixup" which works in tandem with
"removed-dma-pool" compatibility that tries to shrink and
adjust the removed area on very first successful allocation.
At end of which it returns the additional (unused) pages
from the region back to the system.
Point to note is this that this adjustment is done on very
first allocation and thereafter the region size is big
enough only to support maximum of first allocation request
size. This fixup is attempted only once upon first
allocation and never after that. Clients can allocate and
free from this region as any other dma region.
As the description suggests this type of region is specific
to certain special needs and is not to be used for common
use cases.
Change-Id: I31f49d6bd957814bc2ef3a94910425b820ccc739
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Upon Diag function bind, the DLOAD memory region should be
updated with the USB PID and serial number in order to support
a persistent connection with the PC if the device reboots into
download mode.
This functionality need not be handled in the android.c driver.
The only reason it is there is to be able to locate the IO address
which is specified in device tree. Since this can be done from
the Diag function driver directly, move the handling there.
The address itself can be specified under the "qcom,msm-imem"
parent with its own "qcom,msm-imem-diag-dload" compatible string.
For now, allow falling back to retrieving the address from the
"android_usb" for backwards compatibility until the device tree
files are updated.
Change-Id: I0d6d1dac0f12b7890220d857227ae45c9258c1f2
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Since the qcom,pshold device now supports up to two
distinct register definitions, add the 'reg-names' property
to assign names to the memory resources, rather than
relying on resource numbering.
Change-Id: Ie0bc5eae0119901239efae05357ae107a112b87a
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Some targets require that the Download Mode / EDL
configuration be performed by means of a Secure I/O write
to the TCSR_BOOT_MISC_DETECT register rather than through a
generic SCM operation. Provide a mechanism for specifying
the address of this register in the device tree, to use as
a fallback method if the generic SCM call to set the
download mode configuration is unavailable.
This is necessary to comply with atomicity requirements of the
secure environment.
Change-Id: I5d3fcb48b0b47815d4839a3b722b0462a1bca087
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of
kernel.lnx.3.18-151201.)
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Add support for QRBTC V2 UFS PHY that is used in msmcobalt rumi platform.
Change-Id: I21ad3f0db23ea16d05ba40593cc7650e1a443702
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Add support for new QCOM UFS PHY that is used in
future platforms.
Change-Id: I53f162738668ae9f24f5edb9c42a17f947e68b40
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Current UFS PM QoS design and implementation do not seem to give
the desired increase in performance. This change revisits the
PM QoS implementation trying to improve performance by making
the following changes:
* de-couple voting from clock scaling decision so voting
occurs from the first request and unvoting on the completion
of the last request regardless to clock scaling state.
Otherwise, suspending the PM QoS voting during the time it takes
to decide on clock up-scaling, seems to degrade random access
performance.
* vote on a per-cluster basis by inspecting the request object's
cpu field. This follows the soft-irq allocation scheme in the
block layer, so the cpu to which the block layer schedules the
soft-irq will not be put into deep LPM.
We should note that PM QoS voting using cpu mask for specific
cpus is a feature of the qcom specific PM QoS implementation.
Change-Id: I427d202aeb45cd284a3bb128e26e519212614801
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
[venkatg@codeaurora.org: resolved merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This is a snapshot of gdsc-regulator documentation as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of
kernel.lnx.3.18-151201.)
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
As of HW major version 2, bit 'UFS_DEV_REF_CLK_EN' which is used to
gate/ungate the ref_clk to external UFS device, was moved into the
UFS register space to UFS_CFG1 register. This change adds support
to appropriately control the device reference clock and it also
adds the missing documentation for the device reference clock control
register address space.
Change-Id: I66a6a75dc5a1cf130b1cee90ae20f9f950edfb3a
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Different platform may have different number of lanes
for the UFS link.
Add parameter to device tree specifying how many lanes
should be configured for the UFS link.
Change-Id: Ida8b13b916f76b3cc7afd3da3d04219e95627678
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
PM QoS request type PM_QOS_REQ_AFFINE_CORES specifies for which CPU
cores the voting is applied to by the cpu affinity mask.
This change defines the cpu mask to be used for the voting in the
device tree node so it can be customized for each target.
Change-Id: I004dea47b42eaf3cdf0489427b2bb894c9982f22
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Add PM QOS cpu-dma latency request to the driver.
Latency parameter value is taken from the device tree node
using an optional parameter 'qcom,cpu-dma-latency-us'.
Unless specified, a default of 200us is used.
Change-Id: I3e10da9e65fc7324897c866b0c2a40cc5e6ca070
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
On Qualcomm platforms, there will be many consumers of the source clock
which also supply ref_clk to UFS Device. So even if generic UFS
driver (ufshcd) vote to turn off the source ref_clk, it's very likely that
device ref_clk is still running. Hence some of the qualcomm chipsets have
separate control bit to gate & ungate the UFS ref_clk to device. This
control bit is part of the TLMM register adddress space so it can't be
simulated at clock control bit which means UFS qcom driver has to manually
control this bit to gate or ungate the device ref_clk. This change adds
support for the same.
Change-Id: I3ee1187292eaadfdb552d33c2bb6f58922c9e501
[subhashj@codeaurora.org: resolved merge conflicts, dropped changes to
msm8994.dtsi]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts,
drop changes to include/linux/phy/phy-qcom-ufs.h]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
UFS device and link can be put in multiple different low power modes hence
UFS driver supports multiple different low power modes. By default UFS
driver selects the default (optimal) low power mode (which gives moderate
power savings and have relatively less enter and exit latencies) but
we might have to tune this default power mode for different chipset
platforms to meet the low power requirements/goals. Hence this patch
adds option to change default UFS low power mode (level).
Change-Id: I45aaae9f46beb3b5d38bcc6dcbd728e79677276c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In this change the "compatible" attribute in dts files of ufsphy node
and the "phy-names" attribute in ufs node are changed to a more generic
name.
This is done for apq8084 and for msm8994 targets.
Change-Id: I46176459e9bc877456489e4728b86eecb2c16261
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts & dropped changes to
apq8084.dtsi & msm8994.dtsi]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This re-factor is required in order to provide a robust way to support
multiple ufs phys. It also creates a better separation between
ufs-msm block, ufs-msm-phy block and the specific phy blocks.
In this change a generic phy handle is created, using the phy driver
framework.
Two ufs phys are currently supported: 28nm and 20nm
This change also includes the required DT changes as in this case,
the driver changes and the DT changes must be placed within the same
change.
Change-Id: I3aa7ed942ed7b54f3a29c9b9dbdeff1861079066
Signed-off-by: Noa Rubens <noag@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[gbroner@codeaurora.org: fix merge conflicts in apq8084 and msm8994
device tree files]
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts, dropped changes to
msm8994.dtsi and fixed compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The UFS host controller on MSM chipsets transfer data over
System NoC to the DDR memory. Add bus bandwidth voting support
based on the speed modes the host communicates with the device
so as to provide optimum throughput while transferring data over
the bus.
Change-Id: I1b407975984985fa108aa9373e2eab08b9027df4
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[gbroner@codeaurora.org: fix merge conflicts - apq8084.dtsi file
location has been previously changed and is already up to date]
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts and also fixed
compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add MSM UFS host PHY driver which binds with UFSHCD platform
driver exposing vendor specific operations to initialize the
PHY. Since the controller and PHY are tightly coupled in the
system, some of the MSM specific controller register
configuration is also applied inline while initializing PHY.
Add a new compatible property "qcom,ufshc" which specifies the
UFS host controller on MSM platforms. The UFS controller driver
binds with UFS PHY driver using the phandle reference of PHY
devicetree node.
Change-Id: If695a844d03268151c6c846bdfa6cee8ff84491b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The system crashes due to bad access when reading from an non configured
peripheral and when writing to peripheral which is not owned by current
ee. This patch verifies ownership to avoid crashing on
write.
For reads, since the forward mapping table, data_channel->ppid, is
towards the end of the block, we use the core size to figure the
max number of ppids supported. The table starts at an offset of 0x800
within the block, so size - 0x800 will give us the area used by the
table. Since each table is 4 bytes long (core_size - 0x800) / 4 will
gives us the number of data_channel supported.
This new protection is functional on hw v2.
Change-Id: I74e3452963a7dda9a8c8aaef76de3117cabc454b
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current driver uses irq_read_line api which is not standard.
Instead use a gpio and register for an interrupt when it changes
states. And upon a change in state interrupt is received, read the
gpio state to determine whether it is high or low.
Change-Id: Ie4b1226cedfb44e65a84349da4b3eef5fe988dff
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
This is a snapshot of the SPM driver from 3.18 kernel. The upstream spm.c
file is used as a idle driver. So updated spm driver from 3.18 kernel to
msm-spm.c on 4.4 kernel.
Change-Id: I73b020214fdcc7eb695cf8f5b52cf7885a0a10cd
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Change to using upstream spmi bus architecture. All the spmi devices,
marked by spmi-dev-container, become platform devices.
spmi-slave-container devices become spmi_devices each representing
a slave. The read/write functions use regmap api's instead of calls to
spmi_ext_register_read/write() implemented by the spmi bus. This
regmap is instantiated per slave.
The spmi bus helper functions like spmi_get_irq get changed to their
platform bus equivalents.
Change Kconfig files include
* Remove dependence on OF_SPMI, MSM_QPNP_INT
* There were few places where an earlier commit
dcc2aedc80746acee589e4b47d3e6adf5d3ec253
missed adding dependence on SPMI along with MSM_SPMI.
Fix them.
* Add depends on ARCH_MSM. ARCH_MSM is used for internal builds.
Change the nodes in DTSI files to confirm to the modified drivers.
Update their binding docs to drop spmi-dev-container and
spmi-slave-container;
Finally update defconfig to use upstream SPMI.
Change-Id: Ic85bff27c09c84b152cb38acbc3cadd05c0ec57a
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
