commit 23ca9b522383d3b9b7991d8586db30118992af4a upstream.
kernelci reports a failure of the ip28_defconfig build after upgrading its
gcc version:
arch/mips/sgi-ip22/Platform:29: *** gcc doesn't support needed option -mr10k-cache-barrier=store. Stop.
The problem apparently is that the -mr10k-cache-barrier=store option is now
rejected for CPUs other than r10k. Explicitly including the CPU in the
check fixes this and is safe because both options were introduced in
gcc-4.4.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15049/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit ea58fca1842a5dc410cae4167b01643db971a4e2 upstream.
Since linux-4.3, SCSI_DH is a bool symbol, causing a warning in
kernelci.org:
arch/mips/configs/ip27_defconfig:136:warning: symbol value 'm' invalid for SCSI_DH
This updates the defconfig to have the feature built-in.
Fixes: 086b91d052 ("scsi_dh: integrate into the core SCSI code")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15001/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit b617649468390713db1515ea79fc772d2eb897a8 upstream.
One of the last remaining failures in kernelci.org is for a gcc bug:
drivers/net/ethernet/qlogic/qlge/qlge_main.c:4819:1: error: insn does not satisfy its constraints:
drivers/net/ethernet/qlogic/qlge/qlge_main.c:4819:1: internal compiler error: in extract_constrain_insn, at recog.c:2190
This is apparently broken in gcc-6 but fixed in gcc-7, and I cannot
reproduce the problem here. However, it is clear that ip27_defconfig
does not actually need this driver as the platform has only PCI-X but
not PCIe, and the qlge adapter in turn is PCIe-only.
The driver was originally enabled in 2010 along with lots of other
drivers.
Fixes: 59d302b342 ("MIPS: IP27: Make defconfig useful again.")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15197/
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 9ddc16ad8e0bc7742fc96d5aaabc5b8698512cd1 upstream.
In linux-4.10-rc, NF_CT_PROTO_UDPLITE and NF_CT_PROTO_DCCP are bool
symbols instead of tristate, and kernelci.org reports a bunch of
warnings for this, like:
arch/mips/configs/malta_kvm_guest_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
arch/mips/configs/malta_defconfig:62:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP
arch/mips/configs/malta_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
arch/mips/configs/ip22_defconfig:70:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP
arch/mips/configs/ip22_defconfig:71:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
This changes all the MIPS defconfigs with these symbols to have them
built-in.
Fixes: 9b91c96c5d1f ("netfilter: conntrack: built-in support for UDPlite")
Fixes: c51d39010a1b ("netfilter: conntrack: built-in support for DCCP")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14999/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 7d6e9105026788c497f0ab32fa16c82f4ab5ff61 upstream.
An ancient gcc bug (first reported in 2003) has apparently resurfaced
on MIPS, where kernelci.org reports an overly large stack frame in the
whirlpool hash algorithm:
crypto/wp512.c:987:1: warning: the frame size of 1112 bytes is larger than 1024 bytes [-Wframe-larger-than=]
With some testing in different configurations, I'm seeing large
variations in stack frames size up to 1500 bytes for what should have
around 300 bytes at most. I also checked the reference implementation,
which is essentially the same code but also comes with some test and
benchmarking infrastructure.
It seems that recent compiler versions on at least arm, arm64 and powerpc
have a partial fix for this problem, but enabling "-fsched-pressure", but
even with that fix they suffer from the issue to a certain degree. Some
testing on arm64 shows that the time needed to hash a given amount of
data is roughly proportional to the stack frame size here, which makes
sense given that the wp512 implementation is doing lots of loads for
table lookups, and the problem with the overly large stack is a result
of doing a lot more loads and stores for spilled registers (as seen from
inspecting the object code).
Disabling -fschedule-insns consistently fixes the problem for wp512,
in my collection of cross-compilers, the results are consistently better
or identical when comparing the stack sizes in this function, though
some architectures (notable x86) have schedule-insns disabled by
default.
The four columns are:
default: -O2
press: -O2 -fsched-pressure
nopress: -O2 -fschedule-insns -fno-sched-pressure
nosched: -O2 -no-schedule-insns (disables sched-pressure)
default press nopress nosched
alpha-linux-gcc-4.9.3 1136 848 1136 176
am33_2.0-linux-gcc-4.9.3 2100 2076 2100 2104
arm-linux-gnueabi-gcc-4.9.3 848 848 1048 352
cris-linux-gcc-4.9.3 272 272 272 272
frv-linux-gcc-4.9.3 1128 1000 1128 280
hppa64-linux-gcc-4.9.3 1128 336 1128 184
hppa-linux-gcc-4.9.3 644 308 644 276
i386-linux-gcc-4.9.3 352 352 352 352
m32r-linux-gcc-4.9.3 720 656 720 268
microblaze-linux-gcc-4.9.3 1108 604 1108 256
mips64-linux-gcc-4.9.3 1328 592 1328 208
mips-linux-gcc-4.9.3 1096 624 1096 240
powerpc64-linux-gcc-4.9.3 1088 432 1088 160
powerpc-linux-gcc-4.9.3 1080 584 1080 224
s390-linux-gcc-4.9.3 456 456 624 360
sh3-linux-gcc-4.9.3 292 292 292 292
sparc64-linux-gcc-4.9.3 992 240 992 208
sparc-linux-gcc-4.9.3 680 592 680 312
x86_64-linux-gcc-4.9.3 224 240 272 224
xtensa-linux-gcc-4.9.3 1152 704 1152 304
aarch64-linux-gcc-7.0.0 224 224 1104 208
arm-linux-gnueabi-gcc-7.0.1 824 824 1048 352
mips-linux-gcc-7.0.0 1120 648 1120 272
x86_64-linux-gcc-7.0.1 240 240 304 240
arm-linux-gnueabi-gcc-4.4.7 840 392
arm-linux-gnueabi-gcc-4.5.4 784 728 784 320
arm-linux-gnueabi-gcc-4.6.4 736 728 736 304
arm-linux-gnueabi-gcc-4.7.4 944 784 944 352
arm-linux-gnueabi-gcc-4.8.5 464 464 760 352
arm-linux-gnueabi-gcc-4.9.3 848 848 1048 352
arm-linux-gnueabi-gcc-5.3.1 824 824 1064 336
arm-linux-gnueabi-gcc-6.1.1 808 808 1056 344
arm-linux-gnueabi-gcc-7.0.1 824 824 1048 352
Trying the same test for serpent-generic, the picture is a bit different,
and while -fno-schedule-insns is generally better here than the default,
-fsched-pressure wins overall, so I picked that instead.
default press nopress nosched
alpha-linux-gcc-4.9.3 1392 864 1392 960
am33_2.0-linux-gcc-4.9.3 536 524 536 528
arm-linux-gnueabi-gcc-4.9.3 552 552 776 536
cris-linux-gcc-4.9.3 528 528 528 528
frv-linux-gcc-4.9.3 536 400 536 504
hppa64-linux-gcc-4.9.3 524 208 524 480
hppa-linux-gcc-4.9.3 768 472 768 508
i386-linux-gcc-4.9.3 564 564 564 564
m32r-linux-gcc-4.9.3 712 576 712 532
microblaze-linux-gcc-4.9.3 724 392 724 512
mips64-linux-gcc-4.9.3 720 384 720 496
mips-linux-gcc-4.9.3 728 384 728 496
powerpc64-linux-gcc-4.9.3 704 304 704 480
powerpc-linux-gcc-4.9.3 704 296 704 480
s390-linux-gcc-4.9.3 560 560 592 536
sh3-linux-gcc-4.9.3 540 540 540 540
sparc64-linux-gcc-4.9.3 544 352 544 496
sparc-linux-gcc-4.9.3 544 344 544 496
x86_64-linux-gcc-4.9.3 528 536 576 528
xtensa-linux-gcc-4.9.3 752 544 752 544
aarch64-linux-gcc-7.0.0 432 432 656 480
arm-linux-gnueabi-gcc-7.0.1 616 616 808 536
mips-linux-gcc-7.0.0 720 464 720 488
x86_64-linux-gcc-7.0.1 536 528 600 536
arm-linux-gnueabi-gcc-4.4.7 592 440
arm-linux-gnueabi-gcc-4.5.4 776 448 776 544
arm-linux-gnueabi-gcc-4.6.4 776 448 776 544
arm-linux-gnueabi-gcc-4.7.4 768 448 768 544
arm-linux-gnueabi-gcc-4.8.5 488 488 776 544
arm-linux-gnueabi-gcc-4.9.3 552 552 776 536
arm-linux-gnueabi-gcc-5.3.1 552 552 776 536
arm-linux-gnueabi-gcc-6.1.1 560 560 776 536
arm-linux-gnueabi-gcc-7.0.1 616 616 808 536
I did not do any runtime tests with serpent, so it is possible that stack
frame size does not directly correlate with runtime performance here and
it actually makes things worse, but it's more likely to help here, and
the reduced stack frame size is probably enough reason to apply the patch,
especially given that the crypto code is often used in deep call chains.
Link: https://kernelci.org/build/id/58797d7559b5149efdf6c3a9/logs/
Link: http://www.larc.usp.br/~pbarreto/WhirlpoolPage.html
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11488
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2e46565cf622dd0534a9d8bffe152a577b48d7aa upstream.
A recent change claimed to fix an off-by-one error in the OOB-port
completion handler, but instead introduced such an error. This could
specifically led to modem-status changes going unnoticed, effectively
breaking TIOCMGET.
Note that the offending commit fixes a loop-condition underflow and is
marked for stable, but should not be backported without this fix.
Reported-by: Ben Hutchings <ben@decadent.org.uk>
Fixes: 2d380889215f ("USB: serial: digi_acceleport: fix OOB data sanity
check")
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2d380889215fe20b8523345649dee0579821800c upstream.
Make sure to check for short transfers to avoid underflow in a loop
condition when parsing the receive buffer.
Also fix an off-by-one error in the incomplete sanity check which could
lead to invalid data being parsed.
Fixes: 8c209e6782 ("USB: make actual_length in struct urb field u32")
Fixes: 1da177e4c3 ("Linux-2.6.12-rc2")
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Return EINVAL if cmd is not v4l2 PRIVATE_IOCTL_CMD.
Change-Id: Iaffa0f2062ea9832dfbaf58a5477185721ff0046
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
Add support for 192k/96k sampling rates for HPH RX
on SDM660 internal codec.
Change-Id: I364cdfc1b3e086158b6d115b7e4c4ddaf5c132b1
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Recommendation is to use NOMINAL in stead of TURBO
clock as threshold for voting with CX iPeak.
Change-Id: Idcdc9ee86118a34a031b80dc86f7cc6dad71a05f
Signed-off-by: Srikanth Uyyala <suyyala@codeaurora.org>
WLAN firmware responds with number of memory regions and starting
address of each as part of MSA info response. These memory
regions needs to be assigned with different hypervisor permission
based on secure_flag. Current code assumes that there will always
be 2 regions passed by WLAN FW but WLAN FW may pass only one
region to be mapped. Map the memory region based on number of
memory region passed by WLAN FW.
Change-Id: Ib62570a0851adb858b0f11959265ea9c0b42429e
CRs-fixed: 2021566
Signed-off-by: Prashanth Bhatta <bhattap@codeaurora.org>
int_count variable datatype is uint64 in tz version 2.X/3.0, and
is changed to uint32 in tz version >=4.X, so updating int_count
according to the TZ version.
Change-Id: I72e128e6ad41711fd49416faf6aebfc869187ee2
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Endpoint command to request resources on ep0 is take upto ~800us and
this delay is observed for every new/re enumeration. As the api polls
(reads the register and it happens over cnoc) for every 1us to check
for completion it could result in congestion on cnoc. Hence increase
polling interval from 1us to 20us for this endpoint command.
Change-Id: I6d738b46a47b00105289e8f07b8fe0883a3fda44
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
There is a possibility of port change event triggering
xhci irq as soon as halt bit is cleared in xhci_start().
As a result before xhci state is changed from XHCI_STATE_HALTED
to 0 port change event keeps on generated until port status is
acknowledged. This does not allow xhci_start() to finish and handle
the port change event if irq is keep on getting fired on same core
where xhci_start() is running. Fix this issue by disabling irq before
starting controller and enable it back after clearing halt bit.
Change-Id: I798620f99a7ba522258455642e6e8091ebf2cd34
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
mhi clients can manage both hardware and software event rings.
Process incoming data based on event ring type instead of
channel type.
CRs-Fixed: 2018326
Change-Id: Ifa2de76034224c19a846f7be153400888f8c66de
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
When a client ask MHI host to processed X number of events, only count
transfer events as part of processed events. All other events are internal
events.
CRs-Fixed: 2018324
Change-Id: I4cfcae0ba187348442c3fc45b76d7c4b01f687bd
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Since the PTE shareability values can be multibit fix so that they
are properly checked.
Change-Id: I36791921b0189b50cbbcb79efdb2f1a36ad9d726
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Fix the symbol linking error for loadable kernel modules
which is using secure buffer hypervisor api for smmu configuration.
CRs-Fixed: 2019262
Change-Id: I3d83fd4b1854298c1283e03f220de8c673195492
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
gsi_reg.h file includes the definitions of GSI registers.
The GSI Instruction RAM registers are defined twice.
This change removes the duplication.
Change-Id: Iccd256711c28a5f4698555079a7f73ce0357a92d
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
Increase the common CMA region size to 44MB to accommodate modem diag
buffer region.
Change-Id: Iad83f749d8ca5635ead9c637dbc2f927191414fe
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
For sdm660 the ULPS clamp registers are moved from
DSI PHY level to interface level. This change handles
the new settings for both video mode and command mode
interface.
Change-Id: Ib99c605362aa25aacfa394c1a7ffe2886acf7035
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
If both irq chip and external interrupt controller implement
irq_disable callback then disable_irq() API disables an interrupt
at external interrupt controller level but does not disable at GIC
level due to lazy approach. During the cpu hotplug gic_set_affinity()
checks whether IRQ enabled at GIC level or not and enabling IRQ at
external interrupt controller level too after IRQ migration to new cpu
even though IRQ was disabled. So add a check in gic_set_affinity()
to check whether IRQ was disabled in descriptor before enabling.
Change-Id: Iba81881c08102ac0a5960c3a97c1c9f8c477bd56
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
As per the hardware documentation, update the regulator
configuration for apc0, apc1, gfx CPR regulators to support new
speed bins in msm8996pro.
CRs-Fixed: 1083423
Change-Id: I97b9b98305e3478012664b636df26299eca66f26
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add a VDD_APCC CPR boost corner of 1996.8 MHz for the power
cluster on MSM8996-Pro speed bin 1 parts.
Change-Id: I9bf29cdba47918770dbef5cd1f2631afccf26221
CRs-Fixed: 1010722
Signed-off-by: David Collins <collinsd@codeaurora.org>
Change the MinSVS fuse corner to virtual corner mapping for the
power cluster and performance cluster on MSM8996-Pro chips with
CPR fuse revision 2 or greater.
Change the mapping according to the following:
Power cluster: 1 (307.2 MHz) --> 3 (460.8 MHz)
Perf cluster: 1 (307.2 MHz) --> 4 (537.6 MHz)
Change-Id: I6b6ee6225d43605ad0f5ae1e16061acf12b49927
CRs-Fixed: 1004373
Signed-off-by: David Collins <collinsd@codeaurora.org>
Update the VDD_GFX CPR open-loop and closed-loop voltage
adjustments for MSM8996-Pro chips based upon characterization
results. This ensures stability and minimum power consumption.
Change-Id: I89b79f92bcb4cc54a050f8b0ba17f76ff471838f
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
Set the CPR IRQ affinity of the VDD_APCC CPR3 controller to be
both cores of the APPS power cluster (i.e. CPU0 and CPU1). This
ensures that neither of the CPU cores of the performance cluster
will be woken up to service a VDD_APCC CPR IRQ which was
generated when the last performance cluster core power collapsed.
Change-Id: I055e50ffcb85622ddd67d55b44d77c342e9ec074
CRs-Fixed: 949650
Signed-off-by: David Collins <collinsd@codeaurora.org>
core_ctl module no longer hotplug the CPUs. Hence remove the
/sys/devices/system/cpu/cpuX/core_ctl/cpus file interface which
pints the online/offline state of all CPUs in the cluster.
The global_state file interface can still be used to know all
the state information about all CPUs. Replace "Active" with
"Isolated" string in this file output. Otherwise we see that
an offline CPU as active.
Change-Id: Id6ffb1c3ddfe85cf34ab670ceea8b53e5b2f60e2
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
We use pr_* to print info/warn/error messages. Use pr_fmt so
that the messages are prefixed by "core_ctl:" string.
Change-Id: Icc84db30ebf0855599431366d090a2b1c94da6d0
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
The online state is cached in CPU hotplug callbacks. This is
used in determining the potential candidates for isolation or
unisolation. The current code has checks in hotplug notifier
callback to correct the online state if it is out of sync
with the actualy CPU state. All this maintenance can be
avoided by directly using cpu_online().
This patch fixes an incorrect warning message emitted from
CPU_UP_CANCELED event callback.
Change-Id: I9681ce6c5bc701507427d60db397ca4966fbdb58
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Hardware characterization has shown that the CPU LDOs can
operate safely with less than 150 mV of headroom voltage.
Reduce the CPU LDO minimum allowed headroom voltage for both the
power cluster and the performance cluster in order to save power
by allowing LDO usage in more situations.
Change-Id: I72f28569d4719540fc84cf65d8783bbfec9435ad
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
Use dedicated rx completion object for DMA transfer mode.
Currently a single completion object is being used for tx, BAM
driver can signal for tx complete while there can be rx process
in active stage. Resulting in BAM_ERROR_IRQ for the pipe connect
as part of the next BAM transfer. Use rx completion callback to
wait for BAM to complete rx transfer.
Change-Id: I65677ed0791c231622a0c33b44f619675a3d8f93
Signed-off-by: Shrey Vijay <shreyv@codeaurora.org>
Update the VDD_APCC CPR open-loop and closed-loop voltage
adjustments for MSM8996-Pro based upon characterization results.
This ensures stability and minimum power consumption. Reuse the
CPR revision 1 adjustment values for future CPR revisions (2 - 7)
for forward compatibility.
Change-Id: I42f7b696987102a38db324a1c515f1c6f01e6d45
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
As per msm8953 design, APM state machine could take more
than 200us for mode switching. Increase SW timeout constraint
value to 500us.
Also, update the mask used to check APM switch status.
CRs-Fixed: 992695
Change-Id: Ie0f8733fb5b39172fb14547292cbd05689a50230
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
The commit 639277b6c73c ("regulator: spm-regulator: Add additional
settling delay for FTS2.5 SMPS") incorrectly changed the usage
of 'uV' variable. The local 'uV' variable holds the correct voltage
level to be scaled up/down. Use it instead of vreg->uV.
CRs-Fixed: 1036738
Change-Id: I52540237a4db79c149409c6017ffc750b5abddd2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Based on characterization add 70us settling delay on the voltage UP
to account for warm-up time and ramp-up delays for 0-10% and 90-100%
of the voltage value.
On the voltage ramp-down side add the stepper slew-rate delay and
and an additional 70us margin to avoid voltage updates while the
stepper is in progress. This could lead to voltage over/undershoot
due to buck-internal synchronization failure.
CRs-Fixed: 1036738
Change-Id: Id4230be9c4c981758bbf6860bab1f487a3b57f85
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
To accommodate speed bin 2 and fuse revisions associated with it
increase the fuse combo count from 16 to 24. At present, this is
needed for msm8996proAU SOC.
Change-Id: I8555162eab2c6bfead2e0762f28525e0aa56cf10
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
To accommodate speed bin 2 and fuse revisions associated with it
increase the fuse combo count from 16 to 24. At present, this is
needed for msm8996proAU SOC.
Change-Id: Ie781ffda433d491a38695caa5e55ec1ec7ff9b4a
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add panel physical width and height properties to nt35597 truly
video and command mode panel, which will be used to calculate
the DPI of display.
Change-Id: I733eb935f55d7979af4331d7ec4bb31d21e55816
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Temp_adj_en instantaneously reduces the voltage and quotient
when temperature enters into corresponding band which may cause
an aggressive reduction in voltage. Avoid this by not configuring
temp_adj_en bit, this only reduces the quotient and allows CPR to
react to the reduced quotient. Use temp_adj_en bit only when both
temperature based and core count based adjustments are desired.
CRs-Fixed: 1051076
Change-Id: Ia42dbdd095e51bf9b9b7e865c104dcbe8f4219da
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Use scaled gate count (GCNT) for aging measurements to reduce
the noise effect on aging data. The amount of scaling depends
on the noise effect observed in characterization results. Use
a selected scaling factor value to derive the gate count (GCNT)
used for aging measurements.
CRs-Fixed: 1025832
Change-Id: I0eb3fb08d51ddca5cd4c08e26bc83eb9f66fd3ed
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Fix the kw issues in jpeg set driver data and in jpegdma modules.
CRs-Fixed: 2017767
Change-Id: I601245553b8148c9f257d55c42367b0b8612db92
Signed-off-by: Krupal Divvela <kdivvela@codeaurora.org>
Check the validity of pointer before dereference and initialize
uninitialized variables.
Change-Id: Ifad4dd9668db91a18b493e0c7276bf6c193fb680
Signed-off-by: Venu Yeshala <vyeshala@codeaurora.org>
video frame event notification is changed so that events will be raised
for all frames both predicted and non predicted frames and invalidate
pts and dts values for predicted frames. This change is specific to
IoT targets in which only non predicted frames will be decoded
and rendered for performance improvement.
CR's-Fixed: 2005724
Change-Id: I08f648a89eb043938fcc7d3d81e83c3599a2f160
Signed-off-by: Udaya Bhaskara Reddy Mallavarapu <udaym@codeaurora.org>
pwm_free() is called in the driver incorrectly when trying to disable PWM
channel while changing the configuration. pwm_free() checks PWMF_REQUESTED
flag before calling disable() hook. The driver doesn't call pwm_request()
but only calls of_pwm_get() at the probe to get the flag once. The Flag
will be cleared when pwm_free() is called for the first time and calling it
afterwards will simply bailout not calling disable().
Replace pwm_free() with pwm_disable(), this won't cause any issue because
the PWM channel is considered statically allocated to the led devices from
hardware perspective and no need to free it in the driver.
While at it, free the PWM device if any errors when getting PWM
configuration.
CRs-Fixed: 2014600
Change-Id: I373d2a1ac83232ce94933c287b4ebe3f23519c83
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Fix the order of parameters passed into read/write APIs to make
it more readable. While at it, add a pr_fmt() to the driver to
get better log information. Also, change all dev_* APIs to pr_*
APIs for better logging.
Change-Id: Ib19f48ddbaeeb3af483ac472dabb44558a6b9e43
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently MISC_TRIM_ERROR_RC19P2_CLK register is hardcoded to
read the trim error in 19.2 MHz RC clock. However, this can be
located differently in some PMICs. Add support to read it from
misc device as this register cannot be directly accessed from
haptics driver.
Specify the MISC peripheral and the clock trim error register in
haptics for pmi8998 and pm660 so that haptics initial drive code
can be adjusted based on error code properly.
Change-Id: I04d8dbac0f943c65272531647c54d3c1495331e7
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
