If a protocol converter or HUB or a dongle supports multi-function
to support both displayport and USB simultaneously and exposes
pin assignment D as supported one, prefer pin assignment D to be
configured on the ports.
Change-Id: Ia69987c0e15ec5f15a07ca3a0e44174ab6e5feb9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
The current generated link rate in software doesn't
consider fractional values. As a result, for few of
the boundary cases, the calculated link rate is not
correct. Fix this by checking for any fractional values.
Change-Id: I3366b70c7e5bfa2a240aa24f1e0c70b54d686721
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the FRAC_START3 register settings for 5.4 GHz link
rate in Display-Port PLL driver. This is needed for accurate
link and pixel clock values.
Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the MISC settings register according the color
depth and format. Update the MVID and NVID registers
using the M and N values used to configuring
the DP pixel clock.
Change-Id: I67e08d3491fbb7c0960c463cc8f979238b89d818
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Since usleep_range provides better accuracy in
comparison to msleep. This helps in reducing the
latency of host bus resume.
Change-Id: Id22104b9e5b63153731df9eb55759de9a86128c6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
A540v1 and v2 both need to enable the LMLOADKILL quirk for the
GPU.
CRs-Fixed: 1036444
Change-Id: I84243578a1ef2f9948f0c9a8c1c00dc6a31eb579
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL
and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers.
This is done to avoid a VPC corner case with local memory(LM)
which leads to corrupt internal state on A540 and its derivatives.
CRs-Fixed: 1036444
Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Embedded tputs depend on WAN RX desc size, but, every target
has its own limitations of memory and embedded tputs goals.
So, add parameter to configure WAN RX desc size through device tree.
Change-Id: I28c550058dd990c9c8cd368a2677097c7f057ccd
CRs-Fixed: 1081543
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Based on the hardware documentation, update the IMA error
handling and clear sequence. In addition, check for DMA errors
and clear it before SRAM transactions begin. Also, check for IMA
hardware status to run the IMA clear sequence during ima_init and
not just based on IMA exception status alone. This is to help
with FG SRAM access to resume again properly in case of an error
encountered.
Change-Id: I583fa51599a1cbbd029cb45c075429730d2e071b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
