Update the CPU frequency to MEM ACC level mappings for
the gold and silver clusters on MSMCOBALT to match the
recommendations given in the voltage plan.
CRs-Fixed: 1046577
Change-Id: Ia2d375b4c9d53dc4eedaf4983dd0bd1433419d75
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Query buffer from buffer manager based on buf index.
This allows modules to provide a buffer associated
with a particular request and avoids a wrong buffer
from being returned.
CRs-Fixed: 1018651
Change-Id: I206f3fa334d96e9f57fcbd985922a436ed701ff3
Signed-off-by: Krishnankutty Kolathappilly <kkolatha@codeaurora.org>
Signed-off-by: Hariram Purushothaman <hariramp@codeaurora.org>
Support a new OSM sequence which optimizes the number of
instructions required to program MEM-ACC settings and
the APM configuration of the CPUSS. This frees up sufficent
space to implement the DxFSM workaround.
CRs-Fixed: 1043040
Change-Id: I9499497cb558efcf3c73e7145ce65d3f129be696
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Program architectural register 6 with the address of the SPM
core count hysteresis register and architectural register 7
with the up and down core-count SPM hysteresis values. The
sequencer uses this information to ensure stable operation
when CPU retention or power-collapse and cluster collapse
LPMs are enabled.
CRs-Fixed: 1045435
Change-Id: I5e41ce376c694736128ceb051db86f93467fdaea
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Since LowSVS and SVS frequencies share the same ACC settings,
map any frequency in the LowSVS to SVS range to the same ACC
level. By doing so, the OSM device need only support 3 levels
instead of 4 thus saving sequencer instruction space. Also,
update the ACC setting to ensure bit 31 of the last ACC register
in each cluster is set when running at LowSVS/SVS frequencies.
CRs-Fixed: 1021659
Change-Id: I322b9b57ec89f5cdc75336d83010ff89a6bb5726
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Define the APM threshold voltage to be used by the OSM device
to determine the correct APM supply selection for different
DCVS setpoints.
CRs-Fixed: 1021656 1030444
Change-Id: Iebeb45eaa2503bd5be19f00938d0dbec1163c5a5
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support to determine the APM threshold corner via open-loop
voltages in the VDD regulator OPP table. The threshold corner
is used by OSM to determine the APM supply for each DCVS setpoint.
The crossover corner is used by OSM to request a specific voltage
during the APM switch transition.
CRs-Fixed: 1021656 1030444
Change-Id: Iac04f6db8e85b3651a33b6c9bff667365cae891d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for a corner whose open-loop voltage corresponds to the
VDD supply voltage required during an APM switch transition. This
corner is requested by OSM hardware to the CPRh controller when
the VDD supply must be set to a specific voltage to ensure a stable
APM switch procedure. Define a crossover corner of 880 mV for both
VDD_APC CPR devices.
CRs-Fixed: 1021656
Change-Id: Icf4b640ec2c330b0d9721d3494297e2d8445c9b6
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Enable SMMU on IPA3 and put in stage1-bypass mode to
not do the memory mapping.
Change-Id: Id2811c67a423c82201993b3119647a3d4caf4517
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
If we have hit fatal errors and are not able to recover using
a reset, crash the system instead of proceeding and causing
further system failures.
Change-Id: I01820e4e8d3d3b603f16b615ae475095c3a417dd
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Add APIs to send and receive vendor defined messages (VDM) over
USB PD. A handler for a standard or vendor ID (SVID) can register
callbacks to be notified of reception of VDM messages. One
use case is for another kernel driver, such as DisplayPort, to be
able to be notified when an Alternate Mode adapter is connected
to the Type-C port in order to enter modal operation. SVID
handlers should maintain their own state and timer resources
in order to comply with the Power Delivery Specification.
Change-Id: Ibe26e6deeca587f21f8121f6f32cf7cc0a5c3e23
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Enable TMC-ETF as the default sink for CoreSight logging.
Change-Id: Ifc867e83746f51abc8d990a334d3f5642efc9c33
Signed-off-by: Satyajit Desai <sadesai@codeaurora.org>
This is the initial commit from thirt party project.
Git-commit: bedea8a0819fc95acd0222e21e61203c8a08bb16
Git-repo: https://github.com/synaptics-touch/synaptics-dsx-i2c/
Change-Id: I892bc03122b096b43fc7f6b757b1161470597ddb
Signed-off-by: Alexandra Chin <alexandra.chin@tw.synaptics.com>
Signed-off-by: Amy Maloche <amaloche@codeaurora.org>
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
(cherry picked from commit 7d4470e29ce77e62acc14a21210e88207e4692b5)
