This is a snapshot of logged IO accessor functions as the following
commit in the msm-3.10 tree:
'commit acdce027751d5a ("Merge defconfig: arm64: Enable
ONESHOT_SYNC for msm8994")'
Change-Id: I4d52ad23cc40d03d2bae1d3942c8d35543a0d461
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[sramana: Fixied merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
This partially reverts 'commit 702b94bff3 ("ARM: dma-mapping:
remove dmac_clean_range and dmac_inv_range")'
Some MSM drivers still use the dmac_clean and dmac_inv_range APIs.
Bring back the defines and exports for v7 CPUs.
Change-Id: I69017d73da1065a5eeb9c87c899b6a51be5ebfe6
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[sramana: resolved minor merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Set the primary display interface as the DSI device. List the supported
panels and set the preferred primary panel to be nt35597 dual-DSI
(non-DSC) panel on msmcobalt MTP.
Change-Id: I117348084e2bec49d0fcd7eb0b0149fc00ae639d
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Charger drivers can have different operating modes such as standlone, or
parallel slave.
Add a mode variable to support different operating modes.
Change-Id: I885289a1eec68335645912c3ecbbe91a85836647
CRs-Fixed: 1023141
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Votables that are NULL or have already been destroyed need not be
destroyed again. Return immediately when destorying NULL votables.
CRs-Fixed: 1023141
Change-Id: I8e367dbe7acf72471a5a474f0e2a00a4004fcbfb
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The parallel charger does not use voting, therefore register getter and
setter functions need to be created or exposed.
CRs-Fixed: 1023141
Change-Id: I96a4877196be78c0eeecc3fc08419e8990572aaa
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The I2C PMIC Controller is used by multi-function PMIC devices which
communicate over the I2C bus. The controller enumerates all child nodes
as platform devices, and instantiates a regmap interface for them to
communicate over the I2C bus.
The controller also controls interrupts for all of the children platform
devices. The controller handles the summary interrupt by deciphering which
peripheral triggered the interrupt, and which of the peripheral interrupts
were triggered. Finally, it calls the interrupt handlers for each of the
virtual interrupts that were registered.
CRs-Fixed: 975120
Change-Id: I5ebe6d0bcb7c097124ba9b35c56579815dda234f
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
When the MSM PCI-e driver isn't enabled, other code that might rely on
some of its exported interfaces will fail to build. Add some stubs for
this scenario to allow other drivers to build independently of
CONFIG_PCI_MSM.
Change-Id: Ib0f6d0ecfa992e2b8aaae9ab6cea3a2e441f65dd
Signed-off-by: Tony Truong <truong@codeaurora.org>
The ion API requires
" The implicit contract here is that memory coming from the heaps is
ready for dma, ie if it has a cached mapping that mapping has been
invalidated "
In v4.4, passsing device==NULL to any dma operation for arm64 results in
a no-op. Ensure that proper device pointers are used.
Change-Id: Id354f7cf6979aa58621408cfcfbd8ef62015fdbd
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Since the blocking chain notifiers can be called from process context,
the notification must not be sent from within a critical section.
Move the blocking notification outside the critical section.
Change-Id: Ia5679310fc59f25643e7c8d572cc230d262c5937
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
The number of ION buffer that can be locked per channel should be
at least the number of channels.
The Load App request, via the SKP channel, uses an ION
buffer that is locked for application swapping by the remote SPSS.
Change-Id: If6b4340b80b313fda87d648baaa1d78a588079ac
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
Set latency values for PM QoS voting to 70us.
These values should be revisited in case LPM latencies change.
Change-Id: Ib37534eaf15ad76abb800fe3917f9c0a832bd30a
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Validate the existence of pm qos groups before accessing them,
to fix null pointer dereference.
Change-Id: Iddb96afac87cf3e7a1cc48f04b3c550e81bdae4b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In addition to patch 71fcbda0fcddd0 (mmc: sdhci: fix command response
CRC error handling), cmd INDEX and END bit error also needs
to handle the same way as in mentioned patch.
So adding cmd index and end bit error case to it.
Change-Id: I6671bb51259515acb0733ce65be8084716d3bfbf
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
When we get a response CRC error on a command, it means that the
response we received back from the card was not correct. It does not
mean that the card did not receive the command correctly. If the
command is one which initiates a data transfer, the card can enter the
data transfer state, and start sending data.
Moreover, if the request contained a data phase, we do not clean this
up, and this results in the driver triggering DMA API debug warnings,
and also creates a race condition in the driver, between running the
finish_tasklet and the data transfer interrupts, which can trigger a
"Got data interrupt" state dump.
Fix this by handing a response CRC error slightly differently: record
the failure of the data initiating command, but allow the remainder of
the request to be processed normally. This is safe as core MMC checks
the status of all commands and data transfer phases of the request.
If the card does not initiate a data transfer, then we should time out
according to the data transfer parameters.
Change-Id: I73ac950f096fa2e81f29ecb40bdd01153c05891f
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ Fix missing parenthesis around bitwise-AND expression, and tweak subject ]
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org # v4.5+
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Git-commit: 71fcbda0fcddd0896c4982a484f6c8aa802d28b1
Git-repo: git://git.linaro.org/people/ulf.hansson/mmc.git
[riteshh@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Defer the resume of the device until a request actually
arrives, thus mandating the use of the device.
CRs-fixed: 987918
Change-Id: I41cf8908dd0f129c54b941c318e938ad7e9d36c9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Do not resume if deferred resume is enabled.
Only resume when a request is received.
Change-Id: I1eae7dffec97d34b066bb5738c84a7e5a82f68d7
Git-commit: ac9ac6f26904c94e8aec47cab6936dd241c2eb66
Git-repo: git://git-android.quicinc.com/kernel/msm-3.10
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
[asutoshd@codeaurora.org: merge conflicts resolved]
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
A card driver can now specify that the underlying bus should *not*
auto-resume with the rest of the system. This is useful for reducing resume
latency as well as saving power when the card driver is not using the
bus. In the future, we'll add support for manual suspend
Change-Id: I077d7dc9311ff12e6e16de631abeac965c8facd9
Signed-off-by: San Mehat <san@google.com>
Git-commit: b44e6c88fc57e08562ff6b4fd68ba89cc2aa21bc
Git-repo: git://git-android.quicinc.com/kernel/msm-3.10
[asutoshd@codeaurora.org: merge conflicts resolved and
similar changes were updated in a different file; due to
changes in kernel version]
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The charger peripheral has a bit to control Qnovo pulse engine.
Enable it.
CRs-Fixed: 1018090
Change-Id: I2ddea8adf1aa9d999cc2fd3fd4f0e0f830147d4c
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Qnovo device is a pulse engine which works with the smb2 charger device
to charge the battery using pulses. It also provides diagnostic voltage
and current measurements at various points in the pulse train.
CRs-Fixed: 1018090
Change-Id: Ie947cc2c74550c98f64dd028c728afa57723c70f
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Qnovo hardware module controls battery charging pulses. Pulse
characteristics are programmed via sysfs files, this driver
translates those values to register values and writes to appropriate
registers.
CRs-Fixed: 1018090
Change-Id: I2573f719f4b2c2fa9a169659a65433fb834ea74e
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Enable charging by default, but disable it for CDP, RUMI and SIM.
CRs-Fixed: 1024022
Change-Id: Ie713f020201cafe6d815c7da5e87ea1566ac36ad
Signed-off-by: Harry Yang <harryy@codeaurora.org>
When routing DMIC input to ANC block for handset ANC usecase,
codec driver enters an infinite loop attempting to determine
the stream sample rate. Additionally since the noise DMIC is
configured prior to the rest of the usecase, we cannot deterine
the stream sample rate to configure the ANC block for half-rate.
Therefore revert that logic and let ANC block be configured
according to the device tree.
CRs-fixed: 997662
Change-Id: I311ad8f158b0be6e9d6481512860f9fac10afc1f
Signed-off-by: Stephen Oglesby <soglesby@codeaurora.org>
Add the DUMMY network interface and the crypto modules needed
for tunneling in advanced data call scenarios.
ECHAINIV is the default algorithm for CBC which is needed for
setting up a tunnel using XFRM state. Dummy network device is used
to route the IPv6 tunneled traffic when there is no IPv6 route
present on a wireless device. The default route in the dummy
interface routing table will route egress packets.
CRs-Fixed: 1024966
Change-Id: I4706b353e63b044368ea54a8ed74d61dc44dc95c
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Currently DMIC clock is set at 4.8MHz for all sampling rates. For
optimal power, sampling rates <=48KHz should be set to 2.4MHz.
CRs-fixed: 971183
Change-Id: If3076f017d476cfb57fa22b75cc74ed615c8882e
Signed-off-by: Stephen Oglesby <soglesby@codeaurora.org>
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
cmd_interrupt flag is set during first stream's stop in gapless playback
but it is not reset after receiving eos ack. This interrupts second
stream partial drain and eos is sent to client, which leads to session
close causing audio mute. Do not set cmd_interrupt during gapless
transition to fix the issue as no one is waiting for eos.
CRs-Fixed: 1012546
Change-Id: Ibcbdde0ea59ff80a798de0b894c2239899260860
Signed-off-by: Dhanalakshmi Siddani <dsiddani@codeaurora.org>
Moisture detection is needed only for NO jack type.
So disable moisture detection feature for NC Jack.
CRs-Fixed: 1012001
Change-Id: I93f72f18145ddef6a0caf2c59a9af5f23e6e20a3
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Add statistics to know driver status which in turn helps in
debugging issues.
Change-Id: I68fa6f510d55822b01c2ea5062d4876c4420c5f7
CRs-fixed: 1026135
Signed-off-by: Prashanth Bhatta <bhattap@codeaurora.org>
This patch fixes the possible race condition
because of the stray dci_mutex unlock statements.
CRs-Fixed: 1027461
Change-Id: I10f3c6d1e2d3c6e71be04e3206273aad7971a6b5
Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
If the card (which is a eMMC 5.1 complaint card) is scaled down
to HS200, then the current logic in partial_init doesn't invoke
tuning due to these invalid checks.
Change-Id: I1e5cbb6a2dfff129acdb27e27ea090d58197f41c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The CDR is supposed to be enabled only for read commands but
since there is no way it can be done in CQ, disable it completely
in CQ mode.
The CDR gets enabled by default whenever tuning is done in legacy
mode. Hence, make sure to disable it when CQ is enabled or when
CQ is unhalted.
Also note that CDR plays a role only in these bus speed modes -
HS200 and HS400 with enhanced strobe disabled.
Change-Id: Ie3917ac9b573dfef514f82e5073d1c480cd9a71d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add the functionality to disable CDR to
sdhci_cmdq_set_transfer_params() so that CQ driver can
use it appropriately.
Change-Id: I5182b48523e7f9511265fa557433b88224318a23
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The scaling logic for HS400 is triggered when the card timing
mode is HS400 or when the clock rate is MMC_HS200_MAX_DTR. But
this is the same rate used in HS200 mode as well. Due to this,
in HS200 mode also, the card enters into the scaling logic meant
for HS400 which is not correct.
Correct this logic by checking the card timing in addition to the
clock rate in HS400 clock scaling logic.
Change-Id: If6261c0e42178d331184ac605c192d48a76e1e29
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
There are issues with ADMA when used with ICE enabled for tuning
commands. As a workaround, use PIO mode for these commands by
enabling quirk SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING .
Change-Id: I8dbec823938525af90fb990db1bb4b325ee23cba
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Some controllers have an issue using ADMA for tuning commands.
Add a quirk - SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING to use PIO
mode for tuning commands on those host controllers.
Change-Id: Id9625167d7e235fb3a20a6193889c1654b5c0cd8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some controllers need SW to compare the data received
from the card for a tuning command. Enable this quirk -
SDHCI_QUIRK2_NON_STANDARD_TUNING for sdhci msm host
controller.
Change-Id: Id6f6230520db1ad018c883cb639fe66b4b86c70c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Some controllers need SW to compare the data received
from the card for a tuning command. Add a quirk for
such non standard controllers so that they can read
the data from the controller using ADMA/PIO and do the
tuning sequence from SW to determine the appropriate phase.
Change-Id: I15edfdf0442e3ac678c70df29482b3304cf1215a
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This is needed to set the dma mode for CQ transfers. The dma mode
may be changed by the commands sent in legacy mode (like tuning
which uses FIFO mode).
Change-Id: Idaa2cb0c7712846f6827272caefc112b127ef818
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some of the transfer parameters like DMA mode will be changed
only when CQ is in HALT state to send some legacy commands like
tuning etc.
Also, fix a typo with set_transfer_params() host op.
Change-Id: I3a9856e0d60ce6a9cc1727cd8ccd10ef33bb707c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Data CRC errors are observed for the data commands that are
sent immediately after tuning in HS200 mode with CQ enabled but
in HALT state. This is because tuning commands change the block
size to 128 bytes from the default 512 bytes.
Change-Id: I9657b16954b54c491fa19f9d82d9141edf45e0ef
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The bkops status is indicated by the bit 0 and 1 of the
246th byte of the ext_csd register.
The current code doesn't ignore the rest of the byte.
Fix this by extracting the bit 0 and 1 only
for the current bkops urgency.
The exception level is defined by the least significant
nibble of 54th byte in the ext_csd register. The current
code doesn't ignore the rest of the byte.
Fix this by extracting the nibble(LSB) for exception status.
Change-Id: Ic90fe26a676ae7dd2063e17bc3771db83605f4dc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
We need to add mmc_host_clk_hold/release pair before caching
host->ios. Since it may so happen that the clks are gated
while caching and thus in next CMD5 awake, changing clk back to
cached_ios->clk might give NOC error.
Change-Id: I32b8c1bbbd67b4daadaa85c3c01beab8ff1b7cb2
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Fix the below reported issues by source code analyzer.
1) Pointer 'ext_csd' returned from call to function 'mmc_get_ext_csd'
may be NULL and will be dereferenced at ext_csd[EXT_CSD_CMDQ] in
mmc_test_awake_ext_csd(), causing NUll pointer derefernce.
2) Array 'sdhci_slot' of size 2 may use index value(s) -1 as below,
when ret = 0.
sdhci_slot[ret-1] = msm_host;
3) Variable 'host->lock' locked ,And was not unlocked when below
condition occurs in sdhci_irq().
if (!mmc_card_and_host_support_async_int(host->mmc))
return IRQ_NONE;
CRs-Fixed: 1000387
Change-Id: Iec6ecef1bf940e720c871be58b265394904f0cf1
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
This reverts 'commit d49beb9a2a71 ("mmc: sdhci: Panic
after SDHC registers")'. As CMDQ is quite stable now,
removing a BUG_ON which was added internally to crash
system on error.
Change-Id: Ie0c11743fb781e765c926e3408b87eaf94dc2eb6
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The scaling down sequence requires the clock to be set
after selecting the corresponding bus-speed mode in the
controller.
The scaling up to HS400 requires the timing and clock to
be set to legacy.
Without the above configuration, bus-width switch fails,
further leading to CRC errors.
Change-Id: If502f28e19924264dfb99d76f6881d3167f56a05
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
For v8/arm64 platforms the number of address-cells can be 2.
If the same device tree is used on 32-bit platforms,it is
currently reading only one cell of 32-bits.
Fix this by reading both cells for getting the hwid.
Change-Id: Id281b6b8ac3c9312848c39e11019284f970caced
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
User space can send the commit message with the dest scaler
structure populated and dest scaler count as 0, this would
cause null pointer access, this change adds validation for both
the fields.
Change-Id: I7a4ad3188f7a19427c096a596a502debdc2aac55
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
