Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.
CRs-Fixed: 1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
MHI transaction status stores the OVERFLOW status
received from device. MHI clients uses this
status to determine overflow buffers, do
not clear the status.
CRs-Fixed: 1042516
Change-Id: Iaaff06c1c39775d6a33ca17851f1e1579b2a2ecb
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
When checking for available spaces, check available spaces on
both bounce buffer ring and transfer ring and return min.
Change-Id: I9208b46c32821de3f5d9e3d828087d7bc29b9546
CRs-Fixed: 1055681
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add missing state MHI_STATE_RESERVE to MHI states
look up table.
CRs-Fixed: 1049595
Change-Id: I9a6bd2750f81f6cabc1e7b5aff488b4a01f7897d
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
When exiting low power modes (M3) do not reset
the DB Mode state if DB mode preserve flag is
set for channel.
CRs-Fixed: 1022868
Change-Id: I6557d28afe9d0ac11b76c683ffba76d7d6ffd377
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
In order to avoid being out of sync between MHI client
and MHI host, host shall not reset the doorbell modes for
hardware channels during MHI_M3 state transition abort.
CRs-Fixed: 1023725
Change-Id: I6c742fc968fd57d71a86039bf1f3f65b1362bc90
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
To avoid any race conditions between MHI_M2 state
transition and MHI_M3 state transition lock the
entire MHI_M3 transition using xfer_lock.
CRs-Fixed: 972390
Change-Id: I7c2e1b7b3966dc5fb8bf2f91bce734bbc58c6fd7
Signed-off-by: Tony Truong <truong@codeaurora.org>
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
There are instances when MHI channel context read
pointer can be accessed simultaneously by different
CPU cores. To make sure read pointer updates visible
to all cores, add a memory barrier after completion
of MHI ring operation.
CRs-Fixed: 966338
Change-Id: Ifc8c4cd7595fed9049009c42420a665fb170079f
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Matt reported that we have a NULL pointer dereference
in ppp_pernet() from ppp_connect_channel(),
i.e. pch->chan_net is NULL.
This is due to that a parallel ppp_unregister_channel()
could happen while we are in ppp_connect_channel(), during
which pch->chan_net set to NULL. Since we need a reference
to net per channel, it makes sense to sync the refcnt
with the life time of the channel, therefore we should
release this reference when we destroy it.
Fixes: 1f461dcdd296 ("ppp: take reference on channels netns")
Reported-by: Matt Bennett <Matt.Bennett@alliedtelesis.co.nz>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linux-ppp@vger.kernel.org
Cc: Guillaume Nault <g.nault@alphalink.fr>
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Git-repo:https://source.codeaurora.org/quic/la/kernel/msm-4.4
Git-commit: 205e1e255c479f3fd77446415706463b282f94e4
Change-Id: Ic7ce3be365ebdc1505ed8ce68df981c855638a3c
Signed-off-by: Srinivasa Rao Kuppala <srkupp@codeaurora.org>
When the GPU hardware init function fails (like say, ME_INIT timed
out) return error instead of blindly continuing on. This gives us
a small chance of saving the system before it goes boom.
Change-Id: Ic0dedbad142efbc9bd93e8531b40c391ec15f557
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Make sure to detach the MMU device before destroying the address
space.
Change-Id: Ic0dedbadff27fed017840a61ec5e0d55ce0c71e6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
SDE and the GPU have different requirements for the SMMU backends - the
SDE generates its own iova addresses and needs special support for DMA
buffers and the GPU does its own IOMMU operations. Add a shim layer to
aspace to break out the address generation and call the appropriate
SMMU functions. There is probably consolidation that can be done, but for
now this is the best way to deal with the two use cases.
Change-Id: Ic0dedbadc6dc03504ef7dffded18ba09fb3ef291
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We can have various combinations of 64b and 32b address space, ie. 64b
CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So
best to decouple the device iova's from mmap offset.
Change-Id: Ic0dedbad2b36b535df3e8fb2ddddc20add592cea
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 22877bcbdacd50d076f9b2f829e6a3753aa9821f
Git-repo: https://github.com/freedreno/kernel-msm.git
[jcrouse@codeaurora.org: Fix merge conflicts, remove mdp5 due to large
infrastructure changes, compile fixes]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Currently, IPA driver asserts if IPA FW loading
fails. Some environments do not have IPA FW
integrated and we should not crash at these cases.
CRs-fixed: 2005599
Change-Id: I78b9f2cadb8c35ab455f4514c7efc9cee4cf4542
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
