Add sysfs entries to allow getting the current status of
PM QoS voting and enable or disable voting.
Change-Id: If5b8e4b155090343112916c9c57a766bb2104e10
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Starting from MCI_VERSION 4.2.0 use a different offset for the following
registers:
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_n
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_WRAPAROUND
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_OVERLAP
In addition, move dump debug ram functionality to the MSM specific file.
Change-Id: I3b0f5101150de9f2c190ce69b306bd151cbb65ae
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Dump crypto related register information during error for
debugging purpose.
Change-Id: I8976e8c0b5e9bda910634464202578dbacd7666e
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for legacy
eMMC.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I5d2b71fc4eabfa5060f343634fbc7363f2ee1344
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for command queueing.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I8a20653eeb6348d5b442c846708d92c8fb64a8e9
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
When encryption/decryption is enabled in CQ mode, the
legacy commands that are sent in HALT state will use
different slot other than slot 0 for crypto configuration
information. The slot that is selected depends on the last
slot that was used when it is in CQ mode. This is causing
the data of legacy commands to be encrypted/decrypted based
on the wrong slot usage for crypto config details. Hence,
clear the crypto configuration of the slot used in CQ mode
whenever it gets completed.
Change-Id: I6817de46d895b61f410dd732be57ba60efb58fb2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add the necessary device tree properties and parsing in the driver
to support PM QoS voting for IRQ and CPU groups for CMDQ / legacy modes.
Change-Id: I1a94978ca66823d2ce78ee230cf36b4ebb72e6d8
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
pm_qos is causing race conditions in CQ mode with
power management. Removing the feature in order to
allow power management.
Change-Id: I340cd784829f389f18df6bff664337aca0f3c867
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Any CMD/DAT errors raised using the error interrupt status in
CMDQ mode also needs to be cleared. If this is not cleared,
any error in supported CMDQ CMD's like CMD 44/45/46/47/48 will
cause an interrupt storm.
Change-Id: Ie725bbf1c859a2dc91b64274e05e71328dfeb1b2
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This patch adds checks in msm host driver to check if card
also supports enhanced strobe before changing strobe specific
host configuration.
Change-Id: Iab4833e80600c4ad89b16c76b52e917f885eea0e
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
When encryption/decryption is enabled in CQ mode, the
legacy commands that are sent in HALT state will use
different slot other than slot 0 for crypto configuration
information. The slot that is selected depends on the last
slot that was used when it is in CQ mode. This is causing
the data of legacy commands to be encrypted/decrypted based
on the wrong slot usage for crypto config details. Hence,
clear the crypto configuration of the slot used in CQ mode
whenever it gets completed.
Change-Id: If573de5025054a10de1dde544aa79022016f65fd
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Update the error code to ENODEV if eMMC is not the boot device.
Change-Id: Ide0863a5aa64f9990d39095de6f6b13f752a6b3e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Use the tag id of the error'd request and don't reset it to zero;
to handle the error'd request appropriately.
Change-Id: I0f5eac47197fa7b59208d0a61776d4ba186aa3dc
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The power on reset value of DDR_CONFIG register was fixed in
controller revision (major - 0x1 and minor > 0x49) to address
the default rclk delay value after characterization. The register
offset for this register was also changed starting from this
revision. Make necessary changes to account for this.
Change-Id: I4e4a87aebd24e5669b03a914c6e0f4b469f5ec7b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In case of a crypto error during request submission clear the
host mrq structure in preparation for the next request and
dump the current register state for further debugging.
Change-Id: I2eeda8589ca4c83bbb4a1b372e9363224bbfb680
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
For any cmd we have a DAT line timeouts which we set in TIMEOUT_CONTROL
register of sdhci. For commands with busy response (R1B), cmd is followed
by a busy period exercised by card, by pulling DAT0 line low
(in case of CMD5). Here host controller detects this busy period and
waits for either busy period to finish or timeout to happen based on
value set in SDHCI_TIMEOUT_CONTROL register.
Thus for R1B commands, host controller(sdhci) is capable of sending
two interrupts. 1st is the CMD response(0th bit - Command complete
of Normal Interrupt Status register ) and 2nd is when the busy period has
ended(1st bit - Transfer Complete bit of Normal Interrupt Status register).
If MMC_CAP_WAIT_WHILE_BUSY is not enabled by the host controller driver
then core layer explictely waits for fixed amount time specified by
s_a_timeout parameter which is generally very high when compared to
amount of time card keeps the DAT0 line low.
As sdhci-msm is capable of detecting this busy period, set
MMC_CAP_WAIT_WHILE_BUSY capability in the host controller driver
to avoid redundant wait period.
On 8952 this saves us ~110ms during mmc suspend.
Change-Id: Ibb3a70575a06a5ffd1ccc3adaa96dfb3c3e22e3a
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
We should keep either one of CDR_EN or CDR_EXT_EN enabled.
So correct this logic in toggle CDR function.
CRs-fixed: 759398
Change-Id: Ic137ae2a28e912ab131644ff9d81e41f4256dd05
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Currently we enable CDR for every read command including
for tuning procedure which is not correct (as CDR if
enabled might correct the phase during tuning and we
wont be able to detect the correct phase during tuning).
So, disable CDR for read tuning commands.
CRs-fixed: 759398
Change-Id: I051b6e3b204dde22cdc973759c3e32d0a81c369a
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
During platform driver probe we call mmc_start_host in sdhci_add_host,
which could start the mmc_rescan work immediately and trigger a runtime
suspend. This creates a race condition where the clocks could be turned off
even before the probe has completed leading to unclocked register access.
CRs-Fixed: 770843
Change-Id: I77ae36f805e496d56ed96db3ccaa83f2c37c926c
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some controllers may not have any LED control to indicate
its status. Use this quirk for such controllers to avoid
registering any LED device with LED class and also to
avoid exposing sysfs nodes which doesn't actually control
any LED.
Change-Id: I7e8f1b8d2d735685ede87df4bb7fb32ad0a10246
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHCI reset for data is getting stuck on some of sdhci-msm
controllers. The SDHCI reset usually waits for any pending transfers
on the bus before proceeding with the controller reset. But in the
failure cases, the data transfer seems to be stuck on the bus and
thus preventing the controller from being reset. The workaround is
to force the controller to be reset under such scenarios. This seems
to be helping the controller to return back to good state at least
for the next commands following the failure.
This issue is found on SDCC5 controller of 8916/8939 and 8992 chipsets.
Hence, enable the quirk SDHCI_QUIRK2_USE_RESET_WORKAROUND only on those
controllers.
Change-Id: Id49009736beb410ccb2535d614786a7c48098f85
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
The SDHCI reset for data is getting stuck on some of sdhci-msm
controllers. The SDHCI reset usually waits for any pending transfers
on the bus before proceeding with the controller reset. But in the
failure cases, the data transfer seems to be stuck on the bus and
thus preventing the controller from being reset. The workaround is
to force the controller to be reset under such scenarios.
This seems to be helping the controller to return back to good state
at least for the next commands following the failure.
Change-Id: I487bdf3bd4afb18e69afa778aa38c3574d69e2f7
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHCI reset for data is getting stuck with the default
MID configuration which uses descriptor requests with MID=0
and data requests with MID=1. This enables interleaving
between MID and is causing reset to be stuck somewhere in the
path DDR<->NOC<->SDHC on few chipsets. Enable one MID mode
as a workaround to this problem which is observed on SDCC5
controller of 8916/8939 and 8992 chipsets.
Change-Id: I12343b35d45774668b7e823ccaa067813fcea4cf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Runtime pm get/put calls need to be called in pairs. Fix the
unpaired call of runtime pm put after input validation.
Change-Id: Ice2ba1e4d17ffde48b2f4d59801bb962f2e9aae7
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
SANITIZE is an operation performed by the storage device and its purpose
is to delete its unmap memory regions.
This change adds support for the SANITIZE capability.
Change-Id: I58b647fb576c694aaa16c1e827d0784d4a5b4456
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
pm qos is currently causing race conditions with runtime pm when
in cmdq mode. Disable this till it is addressed as part of the
pm qos redesign.
Change-Id: I32d04100bbf31995a249188eace164c8761e9141
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Change the rclk delay value to 0.9ns since testing shows
that the valid window may vary for different platforms and the
default value (1.25ns) might fall outside the valid window.
CRs-Fixed: 766702
Change-Id: I6e3522c2764047a773e028078b63e6e94e230d41
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spurious power IRQ which results in system instability.
Change-Id: I1c4f27e131992ef036ebe64fbb2c52613ba396cc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Ensure the task descriptor list memory is flushed before ringing
the doorbell by adding a memory barrier. Also commit the doorbell
write immediately to help improve performance.
Change-Id: I321d5bed95b802d4bcc00836ce9cdede316b29f5
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This is needed to scale up/down the ICE clock during runtime
as per the load on eMMC.
Change-Id: I60d06458767c817298783219caf767866e7bf12f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Switch to using pr_err_ratelimited in order to avoid
flooding the logs in case of error function gets
called repeatedly.
CRs-Fixed: 837631
Change-Id: I08fffb7e77584ac7fe7ba7152677cc12293e1655
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
After issuing a request the usage_count is decremented. After idle time
controller irq is disabled by platform device runtime pm and request
complete irq is not handled.
This change moves decrement of usage_count from the end of issuing request
to the end of request completion.
Change-Id: I1322e0d1ab4ffbf50956fec2921c778e0dcddf36
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
In 3.18 kernel mmc_gpiod_request_cd_irq() is not called as part of
call to mmc_gpio_request_cd(). During probe this is taken care of
by calling mmc_gpiod_request_cd_irq() from mmc_start_host(), but if
mmc_gpio_request_cd() followed by a mmc_gpio_free_cd() is invoked
after mmc_start_host() (such as in system suspend/resume path) then
mmc_gpiod_request_cd_irq() needs to be called explicitly.
Instead of free/request the card detect irq, just disable/enable
the irq in system suspend/resume path.
CRs-fixed: 876453
Change-Id: I976cd5061c2a7d8321e48ee23a44acfd552a37fc
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
CMDQ spec defines periodic SEND_STATUS mechanism to poll
on READY tasks in the device. When DAT lines are in IDLE
the counter counts from its reset value to '0' and then
triggers SEND_STATUS command. When CMD13 is completed and
also the syncing of the device status to HCLK domain is done
there is a 1 cycle pulse to reload the counter with timer
reset value so that the counting can start over.
In rare cases, when the 'done' pulse for reloading the
counter happens in parallel to a BUSY state of direct
command - the IDLE counter is not reloaded and can't
trigger another CMD13. If this scenario happens when
there are pending tasks which are not 'READY' yet - it
can lead to a deadlock, since there is no other mechainsm to
send CMD13, and CQE will never get READY on the pending tasks.
Hence, trigger a send status command after DCMD is completed
as a work-around to the above issue.
Change-Id: I4e8530e72c8bf581ffaeed7d35d8b8c61d282ffa
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Right now only certain amount of delay (146 MCLK cycles as per spec)
is given for card to return back to transfer state upon any CMD error
that host controller may receive. This delay seems to be insufficient
for certain eMMC cards like Hynix. This patch tries to send CMD13 and
also retry it with the same delay to make sure the card is back to
transfer state before sending next command. Otherwise we may see auto
cmd or illegal command failures to the read command sent right after
tuning, especially if the last tuning phase has failed.
Change-Id: I3ec2da150dc5ee656b8156040bf539812b0e4d2b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
There are eMMC cards that should not be powered off
during suspend/resume cycles.
This patch adds support for such cards and avoids powering
the card off during suspend or powering it back on
during resume when MMC_PM_KEEP_POWER is set.
Change-Id: Iec1a0aac80ee41dff56f192e7253c2bd00c15694
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Add MMC_PM_KEEP_POWER specifically when connected to
SDIO cards, rather than in general for the host.
Change-Id: Idb666680f99277ae509c642595821448c21b6c90
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Add call from sdio to host_ops to sdhci_ops
in order to indicate when a sdio card is detected.
This will be used by hosts that require special
handling for card detection.
Change-Id: I65ec6ee464d658cd938d9254a0a748e6137f9223
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The bkops exception handling will ignore cases when
auto bkops is enabled. As such, limiting the enablement
of the exception in cmdq mode to when manual bkops is
enabled yet auto bkops is not.
Change-Id: Icc158cf2c7a2dda6e8b9f1eee8a5924e14330d1f
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
The change in pull configs might not take into effect immediately
and any value read before it is stabilized will mark incorrect
card status. This causes SD card detection to fail when inserted
for the first time. Fix this by adding enough delay after
configuring the GPIO and before reading its value.
Change-Id: I3a8455ce404988ab5eb3ed04c0f90ab6edf76d86
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
When sending CMD during data in HS400 Enhanced Strobe mode,
the command that is being sent is also sampled internally on
CMDIN line by the RCLK that is toggling due to the data traffic.
To mask this <false> CMDIN a new mask is introduced throughout
the CMD transmission time. This mask is controlled by
HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register.
The default reset value of this register is 2.
Before running CMDQ transfers in HS400 Enhanced Strobe mode,
SW should write 3 to
HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register.
Change-Id: If0467855e23cb93e57a4581b375885136902835d
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Provide sdhci host ops of enhanced strobe to notify
sdhci-msm on enabling/disabling cmdq. This is needed
because of following:
Before running CMDQ transfers in HS400 Enhanced Strobe mode,
SW should write 3 to
HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register.
Default reset value of this register is 2.
Change-Id: I987605cd21f137dea49ddf3e8db3f1f41b5b501f
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Provide cmdq_host ops of enhanced strobe to notify
sdhci on enabling/disabling cmdq. This is needed
because of following:
Before running CMDQ transfers in HS400 Enhanced Strobe mode,
SW should write 3 to
HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register.
Default reset value of this register is 2.
Change-Id: I36ead91ca8c9aeed967f120f8bdc3d2180af7746
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
After halting CQE, if other commands are sent in legacy mode,
the timeout would be modified as per the requirements of the
command. Upon unhalting, this timeout would still persist for
CQE too, which in some cases may lead to timeout.
Hence, change the timeout to 0xf i.e. max during unhalt.
Change-Id: Ifb0a1f4b9508c5884d381401216ae6c1373bb7de
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
If eMMC is not a primary bootdevice, there isn't any point of probing
eMMC device hence disable the probing in such case.
Change-Id: I92fa8c2ef373fd8a9140dbfb41356684aaa28e4e
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This reverts commit 9cc95fde7c2c ("mmc: sdhci-msm: enable
clock scaling capability").
Clock scaling is breaking XO shutdown, keep the clock scaling
disabled till that issue is addressed.
Change-Id: Id4c530f8e2a8f565f9b957f46e5086078f808c96
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Add support for handling both manual and auto
bkops when command queuing is running.
Change-Id: Ib967ca3c0420f4e54b3e93c497eb538d7347199a
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
