1. Voltage regulator changes for rear camera
and eeprom.
2. Gpio changes for rear camera and eeprom.
Change-Id: Ie59a748d016211d5ddbab2593ec310a313690f9e
Signed-off-by: Shankar Ravi <rshankar@codeaurora.org>
Currently, there is a possibility that read buffers are
not initialized but diag ends up marking buffers busy and
stops reading from peripheral, which leads to port loss.
Also reset the in_busy variable for the buffer that reads
the data from smd channel when diag smd state is closed.
CRs-Fixed: 1093989
Change-Id: I1990d0ded5a212c9185c149ac297a3630d64bc59
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
Add actuator src and flash src of camera0 node for
support focus and flash function on msm8998 qrd skuk board.
Change-Id: I92ed864aedfdd38c8670e08fb35a6545e8abb142
Signed-off-by: Pengfei Liu <pengfeiliu@codeaurora.org>
Remove msm_bus bandwidth vote from DT for msm8998
as WLAN FW will take care of it.
CRs-Fixed: 1094917
Change-Id: Ied5dcb9e3283dc2ec7f5fd6f03465b070f989d8b
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Modify ACD_EXTINT_CFG so that ACD calibrates every time OSM toggles
full freq signal. This is recommended by hardware guidelines to
prevent ACD from mitigating when CPU clock frequency is boosted.
CRs-Fixed: 1088429
Change-Id: I07856ea8b332dbf12654fdd0b5d5518355f1c350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add mem-acc threshold and crossover voltage properties to the
VDD_APC0/1 CPR devices and a matching mem-acc crossover voltage
to the OSM device. Update the APM threshold voltage
to 800 mV for both clusters.
CRs-Fixed: 1088429
Change-Id: I747fd7665401803998b2824ace6dedbc5797b17f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for configuring the highest memory accelerator
(MEM ACC) threshold voltage. This threshold voltage is used at
runtime to determine which CPRh virtual corner to program into
the OSM sequencer registers in place of the fixed MEM ACC
configuration specified in the OSM LUT.
CRs-Fixed: 1088429
Change-Id: Ida29eaca139c1ddd6439d11a8bd51526366f2a34
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for configuring the memory accelerator (MEM ACC)
threshold voltage and the MEM ACC crossover voltage.
The threshold voltage is used to restrict the floor to ceiling
voltage range of all corners so that they cannot cross the
the MEM ACC threshold voltage due to CPR operation. The
crossover voltage is set when switching the MEM ACC
configuration.
If specified, the APM and MEM ACC crossover voltages are added
to the array of corners after all true corners. If both are
specified, then the APM crossover corner is added before the MEM
ACC crossover corner (i.e. last corner = MEM ACC crossover and
second to last corner = APM crossover).
CRs-Fixed: 1088429
Change-Id: I2b9b746071579ba9d4bcdcfb6cb755ca08a73182
Signed-off-by: David Collins <collinsd@codeaurora.org>
Grabbing the mutex should not be done from netlink_sock_destruct() but
from netlink_release()
CRs-Fixed: 1094434
Change-Id: I69ae0d8589a0878b9758619893848afc272179c5
Signed-off-by: Eric Dumazet <edumazet@google.com>
Patch-mainline: linux-netdev @ 11/26/16, 04:54
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
We want a generic way to insert an RCU grace period before socket
freeing for cases where RCU_SLAB_DESTROY_BY_RCU is adding too
much overhead.
SLAB_DESTROY_BY_RCU strict rules force us to take a reference
on the socket sk_refcnt, and it is a performance problem for UDP
encapsulation, or TCP synflood behavior, as many CPUs might
attempt the atomic operations on a shared sk_refcnt
UDP sockets and TCP listeners can set SOCK_RCU_FREE so that their
lookup can use traditional RCU rules, without refcount changes.
They can set the flag only once hashed and visible by other cpus.
CRs-Fixed: 1094434
Change-Id: Ib4967b801cc5b48c8ac4793b7a03fbfafba2234a
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Tom Herbert <tom@herbertland.com>
Tested-by: Tom Herbert <tom@herbertland.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Git-commit: a4298e4522d687a79af8f8fbb7eca68399ab2d81
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Add support for addtional performance cluster speed bins. Speed bin
fuse 2 and 3 devices can run with a quad core CPU fmax of 2.361 GHz and
single core CPU fmax of 2.457 GHz.
CRs-Fixed: 1086294
Change-Id: I08c3b8bc7e4d40c80be588f05b9439b339f46afc
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0 and VDD_APC1 CPR devices to support two additional
speed bins. This allows CPR operation on bin 2 and 3 parts which have
different performance cluster frequency configurations compared to bin
0 and 1.
CRs-Fixed: 1086294
Change-Id: Id0854f1094ee3e4d4b1961f98a77003f7bcca1da
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The OSM LUT may have duplicate frequencies between one
and four core count compatible frequencies. If the selected
frequency exists for both single and quad core, select the quad
core frequency by default. Also, expose only 4-core frequencies
and the absolute maximum frequency to clock consumers.
CRs-Fixed: 1086294
Change-Id: I2424bfdfd381241d307862113451082a9727a903
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The values written into OSM sequencer registers #55 to #58
correspond to indexes into the CPRh virtual corner table not
indexes into the OSM table. Correct this.
Change-Id: I02baca9a410f08c82c34fe82925c0ead22111e5b
CRs-Fixed: 1086294
Signed-off-by: David Collins <collinsd@codeaurora.org>
The maximum VDD_APC1 voltage has been increased to 1.136 V
for msm8998 v2. Update the AVS limits of L2 SAW and the
CPR aging reference voltage to reflect this.
CRs-Fixed: 1086294
Change-Id: I863bee32e1e66d9656fc70748628b25606b59e47
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Support a total of 32 fuse combos to cater to MSM8998
parts blown with speed-bins 2 and 3.
CRs-Fixed: 1086294
Change-Id: Id03a418f66c9cbb51c2be6904f682d15e82f78c8
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0/1 max floor to ceiling range as well
as the open-loop and closed-loop Nominal fuse corner
adjustments to match the latest hardware characterization.
CRs-Fixed: 1086294
Change-Id: I920175ab16d5a3fc5cd3f117bba3fd1d37db3c5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add the necessary configuration to the OSM clock device in
msm8998 v2 to initialize ACD.
Change-Id: Ibdb861a50ad654be34e14e2bcc012fdf5063acaf
CRs-Fixed: 1053383
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Perform a complete or adequate check of return codes for several
functions, including __qseecom_enable_clk, ion_do_cache_op and
ion_sg_table(), used by qseecom.
Change-Id: Ib1682bdc6d3034a22586af62a3d8986c54d369d5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Add the demo battery profile to support 6A charging with pmi8998
on msm8998 MTP.
Change-Id: Id76ebe4a2591664d44d8003730f70defcb2899bc
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Clone the ascent battery profile to create a demo battery
profile to support 6A charging with pmi8998.
Change-Id: I57d33cadbe26d5298ef7149a004d14102d62f365
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Auto recharge happens when the charging is complete and the
battery SOC or voltage had dropped below certain threshold.
Along with having an option to configure recharge SOC threshold,
a way to configure recharge voltage threshold is required. Add
it. By default, charger is configured to resume charging only
based on the signal from FG based on battery voltage.
Change-Id: I0cd6ca6679c19bbdf4ad980a22d9976396028316
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Clearing the hmp request can cause a task to be freed. When a task is
freed the free call might wake up a kworker which will cause a
spinlock lockup (rq lock). Fix this by avoiding calling put_task_struct
when holding the rq lock.
In addition move call to clear_hmp_request out of stopper thread context
since it is not necessary to do this on the cpu being isolated.
Change-Id: Ie577db4701a88849560df385869ff7cf73695a05
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Allow clients of common clock framework to be able to use the
clock_debug_print_enable API.
Change-Id: Ia8e69dca8c0b84e4daf8ff1f4fb902d11435db76
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The clock nodes require the regulator nodes to be updated for interposer,
so add the same. Also update the gfx rail regulator phandle.
Change-Id: I08580f4eb04660cd1d123065976ba9bfec61b7d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add the new perf configuration for msmfalcon and msmtriton.
Update the msmfalcon_defconfig also.
Change-Id: I8c3be2d0235395a338b758e4dc27a4b243bff62d
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Add property to support multiple sensor which are same slave address
and used in the one platform.
Change-Id: Id6e648ecffd07de1fdafb6fc6187dc14e3e6e36e
Signed-off-by: Wei Ding <weiding@codeaurora.org>
The critical clock handling in __clk_core_init isn't taking the enable lock
before calling clk_core_enable, which in turns triggers the warning in the
lockdep_assert_held call in that function when lockep is enabled.
Add the calls to clk_enable_lock/unlock to make sure it doesn't happen.
Fixes: 32b9b1096186 ("clk: Allow clocks to be marked as CRITICAL")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit ef56b79b66faeeb0dc14213d3cc9e0534a960dee)
Git-commit: ef56b79b66faeeb0dc14213d3cc9e0534a960dee
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: Ifefcbe4741ddd046755ecc24c3f2d619566c2823
Signed-off-by: Taniya Das <tdas@codeaurora.org>
