When rotator fails on a request it would be helpful if information
about the request item was logged.
Change-Id: Ida8b3c9cd312a5142586323b1f9af613a44e40f3
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Add input event handler logic for video mode panels. In case of an
event, the idle notification should be prevented in anticipation of a
frame update.
Change-Id: I28c7b142b3b14375937d45f00fb552679db8f109
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Currently, ESD status check is default to ESD_MAX which
utilizes DSI BTA to perform ESD check as long as ESD check
enabled. Add ESD_NONE as default.
Change-Id: I85713f98a994f71a0e6b7bebe672f1147bd9ac52
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Add support to setup the layer mixer configuration
and select the number of DSC encoders in order to
support different panel configuration modes.
Change-Id: I36dbf8d9e325675bb3affa1794b2fc93ee6151b4
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
[cip@codeaurora.org: Removed dsi .dtsi changes]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Assertive display block can be configured in auto trigger mode,
which removes the requirement of issuing a start calculation
command. Change updates the ad calc worker to remove the kick off
of AD for each vsync and auto trigger mode is made the default mode.
Change-Id: Ie898a595cc9d3c8e521fffc8b3cde240dcbdce0e
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Panels like AMOLED and dsi2hdmi bridge chip does not need
backlight control specified by DSI host. So no need to
fail dsi probe if backlight control is not defined.
Change-Id: I6e192b2e354d6e9146fb0890d2918feab9c7a2ed
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Votes for register bus bandwidth are made from dsi clock manager. Create
separate handles for each dsi controller for bandwidth votes. MDP driver
does not maintain reference counting for register bus bandwidth votes
from each client. Voting from dsi clock manager removes the dependency
on reference counting.
Change-Id: I370053b143b6bc27358844a3958041da59281e92
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
After 'commit 8635960b03b23f9c13c2214ed66cb0d621e7390c
("msm: mdss: refactor MDSS DSI driver")' there is no longer
the need to identify display destination types while reading
the dcs-cmd-by-left property.
Crs-Fixed: 874616
Change-Id: I765c810da1eb4f4bcd5e2c4e585ee7021a6274ee
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Add msm bus scale settings for DSI driver. DSI driver will no longer
piggyback on MDP's bus bandwidth votes for AXI bandwidth.
Change-Id: If4e85c7b399f6e0f1664803d5489831c7b75d751
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
[cip@codeaurora.org: Removed msm8996-mdss.dtsi changes]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
In no panel connected case, when ESD is enabled we see
target is crashing because DSI controller is busy in waiting
for BTA from panel. This causes unwanted DSI PHY errors and
causes target crash due to watchdog bite.
This code change fixes the issue by extending the DSI PHY
recovery mechanism to BTA_TIMEOUT case also.
Crs-Fixed: 863383
Change-Id: I463a5b464cacca9c6c91a989218832aa7198522d
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
During ESD attack, sometimes the panel DDIC might not respond
to the ESD read command. This causes the data lane0 to get stuck
in reverse transmission causing DSI HS FIFO overflow errors
continuously in forward transmission. Enable the error interrupt
generation for LP_RX_TIMEOUT to handle this. Reset the DSI controller
and force DSI lanes to LP-11 to recover from this situation.
Crs-Fixed: 863383
Change-Id: Iee7d5e0c85fb77b9c8f899e569e37b54a100f67a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Address offset was using hardcoded micro tile height of 8; Micro
tile height is not fixed and varies from format to format.
Change-Id: Idd033c955997ce56c64861637c60dd8e6f08c61e
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Attach an input event handler from mdp driver. In static screen cases
with command mode panel, mdp driver will wake up from idle state up on
receiving event from input driver. This will reduce latency during frame
kick off.
Change-Id: I60676915fea6f95a4aad5f49e09123d1a43f70cc
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
In command mode panels, ROIs are manipulated differently based on
multiple factors like source split enabled or not, actual ROI, single
layer mixer, dual layer mixer, single DSI or Dual DSI. Current
implementation doesn't handle dual mixer single DSI configuration
correctly which results in pipeline hang when scaling is enabled. Fix
this by adding a check about this configuration.
Change-Id: Ie4a96948a280450c8f1f0638a55aa06f26063c38
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Fix typo during the off work item; this can cause that
in case of an failure in the driver, the error goes silent
and power resources for the second display context
(i.e. bandwidth and clocks) stay enabled when not needed
without warning for this error.
Change-Id: Iff2683356ef6391ae57b3c5b711b544003584c7c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
This change makes sure that all the clocks held by
the display driver gets disabled when the mdp clock
is also released and will switch the ahb vote to
active-only context, so the bus driver can also
free all the unneeded clocks when cpu is not active.
Change-Id: Id7ee92fdc6e5e91832e4dec61fb151ed20411ef1
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
This change modifies MDP vote to go to Active-Only in
an early stage when bandwidth is not needed and updates
the vote to Active+Sleep when bandwidth must be guaranteed.
Change-Id: I6ccb7a225f97416128518c990d881fa139ec1963
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
When continuous splash handoff is still pending, is not
needed to enable/release the iommu, since clocks and iommu
are already refcounted and enabled.
Add a check so by the time that aplash screen is still
on-going, we do not release the iommu.
Change-Id: I5ea948b2997aeac594f933ddca1096b755473884
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Add support to gate the mdp clocks as soon as the
frame transfer is done for command mode panels.
Change-Id: I8325f26806ff3163edd87b9e3c01cd045f2aec77
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflicts,
use debugfs_create_u32 for enable_gate]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Enable and disable the read pointer interrupt only during
the time that the vsync handlers request this interrupt.
This also makes sure that mdp clocks are enabled during
all this time.
Change-Id: I2564a3b0cf05325c282244f5b60df10d44f5b364
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Add support in the panel interface to apply the requested
events to the panel pointed by the controller only,
this will give the caller the choice to skip the loop
in all the child panels of the interface.
Change-Id: I86edfadb6e326354914b79c284feb10837e83245
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Create a dsi clock manager to control dsi core and link clocks. Clock
manager also has a state machine to transition between ON, EARLY_GATE
and OFF states. Each client will vote for a specific clock state and the
manager will check these votes to maintain lowest possible state.
Change-Id: I50d63f87306cdd650f8d496908716153f0548665
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
[cip@codeaurora.org: Moved new file locations]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Current reg bus vote client supports only single frequency
- 19MHz. This is not sufficient for different use cases like
hist update, pp lookup table update during suspend/resume
scenario. A client may request for higher frequency to finish
the job early and avoid glitches. A client based register
voting allows to traverse through votes from each client
and update register bus vote with max client input.
Change-Id: I4e94d1073375dbd71d9ba6268fc8c548ddb67440
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Only way to swap chroma channels for CrCb formats during writeback
is to swap starting addresses.
Change-Id: I24e72dea5200e1cefc73337117b9f7e44d7994eb
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Client waits for retire fence and reuse the pipe
on another display interface. This pipe is not
stagged on MDP hardware but software structures
are not updated because retire fence is signaled
first. Due scheduling priorities between two threads,
validate call from another interface may come first
and try to reuse the same pipe. MDSS driver fails
this call because software structures are not
updated with pipe status.
Ideally, driver should wait for timeout duration
to allow other interface (or software structure) to
release the pipe. This allow clients to reuse the
same pipe on multiple displays without switching
composition method.
Change-Id: I999874f38a829162de7708cf2e5b3b425c9d5f2a
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflicts]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
During validate ioctl, there is no need to access
some of the registers this early on time.
This patch moves the register programming from
validate to commit, so mdp clocks do not need
to be enabled during validate, preventing
unnecessary toggling of the clocks once those
have been released in command mode panels.
Change-Id: I3eb34221d245153fad14463b873d0b870f5eb62a
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Add support to dump the necessary registers
from the MDP debug bus. And add support to
dump this debug bus for 8994 chipset.
Change-Id: I07f4a4833c8daffb35cd00e6a6c873f35ca2b0c0
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
[cip@codeaurora.org: Resolved conflict on mdss_dump_reg]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
When waiting for an rxstatus message, we need
to ensure that the completion is reinitialized
before waiting for it.
Change-Id: I069b652bf111d79026eed06864ba54934a16db36
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
For destination roi x and y offsets need to be validated for ubwc
formats to make sure that they align to the start of a tile.
Change-Id: I43c50401a212b624851fa0d7f1347fe313d19ca2
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Prevent client from crashing system when wfd_pre_commit is called
without calling validate before.
Change-Id: I83a2b878b300fb835908e57037da8a4d83d114ed
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflict]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Fixes a bug in reading the DSI ROI alignment values as per the
property description.
Change-Id: Ieffa48891f4f9219951b6e90009369db993791a7
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
The HDMI driver is causing an unbalanced
mdss_update_reg_bus_vote call when powering off HPD
in suspend state. Since the DDC module is powered
on for HDCP in MDSS_EVENT_PANEL_ON and then powered
off in MDSS_EVENT_BLANK, there is no need to power
off the DDC module again in the HPD off function.
Change-Id: I3b5e9e352d07e572e6c909554945d949fc374287
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
A limited range IGC LUT is set by default in the cases of HDMI output.
In order to set the default LUTs, the values must be sent according to
the new PP versioning framework. This change adds support for configuring
the IGC parameters according to that framework.
Change-Id: I08e641f9c6dd1be119c98446afad26f633615ea1
Signed-off-by: Benet Clark <benetc@codeaurora.org>
The logic for validating the hardware configuration of the mixers, AD
hardware, and DSPPs in a display pipeline has been simplified. If an
incoming PP configuration is invalid and PP hardware is not available,
a warning is printed. Invalid configurations are recoverable, however.
Change-Id: Ib3a6206a8c181390fb6ee5a6761e5ea857b37e1a
Signed-off-by: Benet Clark <benetc@codeaurora.org>
Pan display commit leaves the left ctl pipe allocated if
right ctl pipe allocation fails. It also tries to release
the iommu refcount when it did not added it. This can lead
to pipe allocation failure for atomic commit or page fault
due to smmu clock disable. This change fixes the error
handling in pan display commit path to release the resources
in correct order.
Change-Id: Icaa0cf164d12fe3f8d4d2012917a5524ad31f824
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
State of dspp histogram blocks attached to logical display
should be changed atomically to idle when histogram collect is ioctl
is called by userspace clients. This will ensure that histogram
interrupt handler will see consistent states for all dspp's attached to
logical display and prevent incorrect sysfs notification to userspace
modules.
Change-Id: I7f32ce21cd65026e1ea01e3b6fe8b571c7b08db3
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
On compatible hardware, HDCP keys can be provisioned
through software instead of being hardware fused.
If HDCP keys are available in sofware, set these
keys and gather aksv through QSEECom calls. If
keys are not available, do not continue HDCP
authentication process.
Change-Id: I7a93b6e1ef958aaa53ef756393ce1f81882bedaf
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Total plane size was not calculated properly for ubwc formats.
Additional the value that this was compared against was also
not calculated properly. This change fixes some minor issues
in data validation.
Change-Id: I0a925f4824bf084e4a7465ecc650ea93936e8f68
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Currently only HDMI driver is using EDID parser. But this parse
can be utilized by other MDSS drivers. Make this as an independent
module which can be used by any other MDSS driver for EDID parsing.
Change-Id: I62622af6c27927b7cf0390238f311452c03cd262
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Enable scrambling for all the pixel clocks where scrambling is mandatory.
Also, do not process multiple interrupts of same HDMI cable status as
this can lead to spin multiple threads, one modifying scrambling data
while other accessing it, resulting in wrong interpretation of scrambling
related data.
Change-Id: I31f80315a7d1b70bc6a0a84f5cd2990021bb8025
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Fix bug in xlog dump which prevents the virtual address
of the registers to be stored in the driver context.
Change-Id: I15fba4b8f88b31b8cd9eb27a21548e04a9a286ff
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Pixel extension block configuration is mandatory
for all pipes and all formats on 8996. It is leading
to underrun if not configured for solid fill format or
other formats. This change configures the software pixel
extension block for all formats - with/without scaling.
Change-Id: Ie724873340c6dfd5e6cb11d66aeb0ac3aae7f841
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
The ability to program default values to the dither hardware
is broken using the new post-processing versioning framework.
This change adds back the functionality of programming the
dither block based on panel bits per pixel.
Change-Id: I016e7ebec3e05107e677d6ca6e2ef7fd078af048
Signed-off-by: Benet Clark <benetc@codeaurora.org>
MDSS driver reports the tile format and ubwc format support
in capability node. It should not report both format
supports because framework may use tile format over ubwc
which is not intended. UBWC is common for venus, camera
and GPU.
Change-Id: If9230d4974ec150d879c77a6f1efba7f040ba2ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflict]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Add csc tables for 601 full, 601 limited and 709 limited
to support different csc matrices.
HAL provides color space request to driver, consider it
to choose appropriate matrix for conversion.
This will help in solving artifacts during GPU/MDP switches
so that both GPU and MDP choose same matrix for conversion.
Change-Id: Idd73e0695ea64d0c0bd778dba07199e209ca6f3d
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Ping Li <pingli@codeaurora.org>
Secure display architecture requires null commit
before and after secure display session. It
also adds requirement to make the SCM call before
and after secure display session. It supports secure
display with single-stage SMMU hypervisor controlled.
Change-Id: I3f41ed318c80d6e76328de114f7dee0c9891c2f0
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
In the current implementation, control register are not being restored
for the compression modes. This causes display corruption on command
mode panels if idle power collapse is enabled. This change restores the
compression mode registers while coming out of idle power collapse.
CRs-Fixed: 859333
Change-Id: Id40270e78b798f3baf7a6c3ad2598f7f12bbf3fb
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
User space needs a way to identify if mdp has UBWC
Change-Id: I5fec34976473ea80c09684d51b14d5588fab09eb
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
