trace_sched_update_task_ravg relies on NULL pointers to ensure that
it doesn't access them. Make sure that when a task exits, these
pointers are set to NULL. Otherwise any call to update_task_ravg()
between sched_exit() and releasing the task structure will access
bogus pointers. In some cases those memory locations are unmapped
and cause a kernel panic.
Change-Id: I9eebb4fb35aca2c8424bfb29ae9d833650dc5ad4
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Device suspend fails because of un-interruptible blocking read
function. Use wait_for_completion_interruptible API instead of
wait_for_completion to allow device suspend.
Change-Id: Ia537e776d0b322d56cd6003f95cdded5e695ceeb
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Enable VDD_GFX CPR aging adjustments for MSMCOBALTv2 parts with
CPR fusing revision greater than or equal to 2. At most 15 mV
can be added onto the open-loop and closed-loop voltage as a
result of an aging measurement at runtime. This maximum 15 mV
adjustment was previously accounted for in the fixed open-loop
and closed-loop voltage adjustments. Therefore, remove 15 mV
from both the open-loop and closed-loop voltage adjustments for
all corners.
Change-Id: I44487bfcb4e21d76948cd836ad2dae18bc3d22f4
CRs-Fixed: 1081084
Signed-off-by: David Collins <collinsd@codeaurora.org>
WCD9335 codec has single master clock supply widget for both
playback and recording paths. Adding separate clock supply
for playback and recording paths will help handle low power
audio recording usecases without affecting playback usecases.
Change is to enable separate clock supply widgets for playback
and recording paths.
CRs-Fixed: 1022917
Change-Id: Ia02a1ffed911498dd6eb5df246e6da68a7802a92
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Update wcd934x codec register defaults to enable
CPR hardware block for reducing the power consumption
in rock bottom sleep mode.
CRs-Fixed: 1081673
Change-Id: Ib75655d52e5d85d649ebfcb971caf3f5b0b6dc80
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Mark CPR bank registers as volatile so that
writes to these registers get updated correctly
in hardware.
CRs-Fixed: 1081673
Change-Id: I92d0511b4e9912dfa346378784d811f6606df205
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Currently, nominal capacity is stored back to the actual capacity
only when the actual capacity is non-zero. However, that can be
true when the battery is inserted for the first time. This makes
the actual capacity to be stored only when a capacity learning
cycle completes. Other algorithms like to use actual capacity
before that. Fix it.
Change-Id: I346085ec722f491f96181ef1beb383710b441f4b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
It is possible that normal CFS latencies in the presence of
very heavy task load causes timer migration to be delayed
in hotplug paths. This may in turn prevent the watchdog kthread
from waking up, resulting in a bark.
Technically the watchdog is supposed to be a last-resort
failure recovery; even in this stressful hotplug scenario
the device is *usable*, just incredibly slow. It is arguable
that the watchdog should not have fired in this case, and
the petting mechanism should handle this scenario.
Move the timer to a deferrable timer base. We are really not
using the "deferrable" aspect of the timer, but the fact that
we (msm) also changed deferrable timers to run on any CPU.
This underlying change will allow the watchdog timer to be
handled on any CPU.
This completely depends on the fact that we don't have to
pet the watchdog when *all* CPUs go idle, which would
make sense from a power perspective anyway.
Change-Id: Ie389e28ff890a805854f921e4cd491a296a32925
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Add NULL pointer check to ensure that we do copy to user only
when we were able to allocate memory for ETR.
Change-Id: I09b4bc37617811fd4acd86a7e4f5ef91630675df
Signed-off-by: Satyajit Desai <sadesai@codeaurora.org>
Currently, smb2 charger is configured to not end the charging
cycle when battery overvoltage occurs. However, when the battery
overvoltage status is read, it will be displayed through health
property. Improve this by reading the battery voltage and check
whether it is within 40mV headroom above float voltage. If it is
above that threshold then continue with displaying overvoltage
status.
CRs-Fixed: 1079363
Change-Id: I45847f446c91c80a5110d80b59a0ae4b8e2c40e5
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Compilation errors are seen from qpnp-pdphy.c and policy_engine.c
drivers, when try to compile for 32 bit support. Hence fix those
errors for 32 bit support getting compiled successfully.
Change-Id: I0c496a73feb83c640f9a135f98ec393d1096b205
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Battery temperature can take negative values. FG driver reads it
as an unsigned value and hence the negative reading is treated as
a huge integer value. Fix it.
CRs-Fixed: 1081146
Change-Id: I63e8863efb91af891dbcbfc070dfdcd833ea3ad4
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently during disabling the EC PP path (Echo cancellation Ping
Pong), the driver is also disabling other data routing controls in
the register. This is causing existing voice activation use-case
using CPE (Codec Processing Engine) to fail as there is no valid
data that is sent to the processing engine. Fix the register sequence
to avoid this issue.
CRs-fixed: 1034169
Change-Id: I2e2b50aeb770ca523cf70e2c0768e38ee56e39eb
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
Add support for CPE(Codec Processing Engine) second voice
wakeup session using ECPP(Echo cancellation Ping-Pong) hardware
path. This allows to enable two concurrent CPE sessions, one
on MAD(Mic Always-on Detection) and the other on ECPP.
Change-Id: I280057b17188757f586562f45f32ecf28595e045
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>
Add additional platform dai for CPE (Codec Processing Engine)
to handle two CPE sessions simultaneously. Change adds another
instance of platform driver.
Change-Id: Id5eee88e87e1e5d68ce34f43b4c85c6b48886b82
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>
Modify the sleep state settings for BLSP1 UART3 pins to optimize power
when the usecase isn't in play.
Change-Id: I1405a8561b1ecb2e3da87ed8b26fb087433a1c11
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Add debug statistics for GSI commands in order to
improve debug capabilities
Change-Id: Iee80fd2bf4b549665a12791009f0cf5ecc7653b9
CRs-Fixed: 1079245
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
The hardware frequency that LMH DCVSh hardware has requested may not
match an actual frequency of CPU. The OSM hardware will aggregate and
match this request to a nearest frequency mentioned in the clock plan.
The current lmh dcvs driver exposes this request without matching to
a frequency value in the OPP table.
In order to reflect the final mitigated frequency, match the mitigation
frequency request from LMH DCVSh to a nearest CPU frequency floor
in OPP table.
Change-Id: Iffc380898eac33f6c30c3808eb38d7bb499f5769
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
