change "iommu/arm-smmu: Support DOMAIN_ATTR_S1_BYPASS"
checks the wrong bit when determine whether to bypass or not
to bypass stage1 translation. Fix it.
CRs-Fixed: 995213
Change-Id: Id347f540f866be6b8442d5f166c6cf7b0ae4c000
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Certain configurations may require nested translation, but may
want to avoid software performance limitation on map/unmap
operations.
Change-Id: I6653b3b6ceb071283fb5a8e07257c496e99dd1f3
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Add support to enable audio functionality on msmcobalt
platform.
Change-Id: Ia06b7877b35c599fdb7a38c09e1cc003d88ec46b
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Add device tree entries of codec and sound node to
have sound card enumeration done on msmcobalt platform.
Change-Id: Icc1ddddfdce35ab1ca70dc68fb4878f7c0c36dc7
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
avtimer is used for synchronization of audio and video
during the playback/capture usecase. Add device tree
documentation for avtimer to explain the device tree
node information.
Change-Id: I625a8970e800487746d458c8f51f63c1b371f08c
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
CPRh controllers communicate voltages to the PMIC via the SAW
AVS interface similar to other controllers supporting hardware
closed-loop operation. Ensure the SPM driver has probed and
enabled the SAW AVS system.
Change-Id: Ide2c4500cfdd0a9c684329ab5f7ac0603e4fc199
CRs-Fixed: 995686
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CPRh communicates voltages to the PMIC via L2 SAW4.
APCLUS{0,1}_L2_SAW4_AVS_CTL/LIMIT registers need to be programmed for
CPRh operation.
CRs-fixed: 987593
Change-Id: I635d710759a94e2bb29fd3c7811816d09243de50
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Add new SAW version v4.1 to support AVS and SPM.
Change-Id: I2187343430efea1dc20523d6e8a5965f360864e6
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
The hmss clocks in the GCC domain should be left enabled
as they are required to be on as long as the CPUs are
active.
Change-Id: If3cc9573debc65018b896f64b1fc85d6a8682168
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Increase the log buf shift in msmcortex and msmcortex-perf to 17.
Change-Id: I920c73ddd2f30c7ab5dd29d3641888fb0f6be61b
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Incorporate the new phy calibration sequence that adds additional
registers and modifies certain calibration data for ufs-qmp-v3 phy.
Change-Id: Id0ac493420a4d076f99b9f0d31b479a50f6eafd2
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In some cases it is useful to manually force the controller
into peripheral, host or disconnect mode. Add a device
attribute to sysfs to do this. Reading it back will indicate
the current mode.
Change-Id: I77d9d2a127a2a763b93b968f1d8ccf68a649493e
Signed-off-by: Jack Pham <jackp@codeaurora.org>
There is no ref_clk selection and switching required on msmcobalt with
USB QUSB PHY. Hence remove usage of phy_clk_scheme.
Change-Id: I755eb9d30f50e30e55382c52aa3471f272fdb4e7
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Currently phy_clk_scheme related information (i.e. cml or cmos) is
used to make decision about how to use ref_clk. On newer platform
this functionality is not required. Hence tie phy_clk_scheme with
availabiliity of ref_clk_base_addr and perform required ref_clk
operation using phy_clk_scheme.
Change-Id: If1f264e155a4411df5e037f9f28bc590e9465ac9
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Fix used register offset and its value with USB QMP PHY.
Otherwise QMP PHY may not initialized as expected.
Change-Id: Ifc23fee9ccecaee738998b957ad5d3fc85094bf6
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
QUSB PHY driver expects to have valid number of bits and bit position
to use efuse based address otherwise it fails QUSB PHY driver probe.
Fix this issue by removing efuse base address with QUSB PHY device
node until valid information is available.
Change-Id: I958e8a2e61c5b4f906d6896ac9696cbb88cd5a69
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change enables u1u2 related low power mode functionality with
super-speed link on msmcobalt.
Change-Id: I5bc5976ec2c0bfb33358614f834db8a7dc7b9e55
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Add QMI message to send MSA0 physical memory start address
and size to wlan FW.
Add QMI message indication to get the HAL-PYH Pin connect test
result from wlan FW.
Add a new qmi message for sending fw debug configuration.
Update cap_resp message.
CRs-Fixed: 978217
Change-Id: Ie0fa374b720ebbffd1d1fd5b9289b2aa816a822a
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Allow child devices to be defined and populated once the OSM
clock device probes. This enables parent and child relationships
across the OSM clock device and any dependent devices.
Change-Id: I0193663d72e05d8227f9814268ec293cfb94bbe3
CRs-Fixed: 994175
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Use secure IO write calls to program the APM crossover corner
and registers 47 and 48 of OSM sequencer architectural space.
Values for these registers reside in the HLOS, but must be
programmed from a secure domain.
Change-Id: I961bde48822adcbfbbb28130f2872104de5c11ce
CRs-Fixed: 992982
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add a debugfs interface to enable and configure OSM debug trace
packet generation. There are four different supported OSM packet
IDs and two tracing modes. The supported sysfs files and their
corresponding values are:
trace_enable [0, 1]
trace_method [xor, periodic]
trace_packet_id [0, 1, 2, 3]
trace_periodic_timer [1 - 20000000] (us)
Unless otherwised modified through trace_periodic_timer, the
default periodic timer is set to 1 millisecond.
Change-Id: I82b7f78bac7379e9a647b5c8e68c356cd1d5c863
CRs-Fixed: 987787
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Remove the qcom,osm-no-tz flag from the OSM clock device
to prevent the clock-osm driver from initializing registers
which are normally programmed by the secure world.
Change-Id: Iadcbba42eeae1f4e8b4a43e0bf833eaa7e96afd5
CRs-Fixed: 992982
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Enable the pulse swallower, droop, WFx, and power-collapse
FSMs to enable all features of the OSM hardware.
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CRs-Fixed: 992982
Change-Id: I69fa6fd84c1e89bb6b698b865dcb9ce1bfc35e98
Refactor the enablement and parameter initialization of the
supported OSM FSMs. This initialization can be performed
by the clock-osm driver in absence of secure-world
initialization.
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CRs-Fixed: 992982
Change-Id: Ie2a78394b388b0357459f1778bb7b2d821abde1c
Support an additional column in the OSM look up hardware table
which establishes a mapping between frequency and mem-acc level.
The OSM uses this mapping to program ACC settings which vary
depending upon the performance level. In addition, update the
OSM sequencer and branch instructions to support ACC programming
as part of the clock scaling scheme and define the mem-acc level
associated with each row of the OSM look up tables.
Change-Id: I03e6f189ab0ab6af406a338bd667fb40240d89b3
CRs-Fixed: 981231
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Move the property overrides defined for the OSM clock CPU device
on the RUMI platform to msmcobalt-rumi.dtsi.
Change-Id: I2f37dc87b3380a1d84b3f2aa1763a47c4ec9b034
CRs-Fixed: 981231
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The vdd and vdd io for SDHC can be turned off when not in use,
hence remove the always on setting and update the supported
voltage levels as per power grid.
Change-Id: I64059e1c440736884c7fea1a0096351b8b49f976
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
IPA Status Packet parsing is a logic related to H/W.
As such, migrate this logic to IPAHAL (H/W abstraction
layer) of IPA driver and adapt the core driver code to
use it. New internal S/W API is added to access the IPAHAL
for Status Packet parsing.
CRs-Fixed: 980623
Change-Id: I5d6a8b8b18de44b0ae512a4610d9f55f538d0fdb
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
There have been some updates to the multimedia clock frequency
plan on MSMCOBALT. Reflect these in the linux clock driver as
well.
CRs-Fixed: 994012
Change-Id: If787e92dbd59b9147d44a53fa3d35d3b3bcfc3d9
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the alpha_pll_set_rate function to support dynamically
updating the pll frequency if the dynamic_update flag is defined
for the pll. Also set the HW_UPDATE_BYPASS_LOGIC bit for these
plls during handoff.
CRs-Fixed: 988270
Change-Id: I7f3527ef45cf68c3f5c41e04bfdd3ede55bbaa4d
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
XO shutdown should not happen when there's still a sleep
vote on DDR. Making CXO as bimc_clk parent takes care of
this.
CRs-Fixed: 992753
Change-Id: I49ac2aefb645a4463cb1873072cd3a1f9a136dad
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add the dynamic_update flag and define the update_mask to enable
MMPLL9 to be able to dynamically update its frequency.
CRs-Fixed: 988270
Change-Id: I48a40f879b07469a954065d568c12e4a75925292
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Add explicit memory barrier after programming USB3_PHY_SW_RESET
register which makes sure that above write is not cached. If
this register write is cached, then phy driver is timing out
with checking PCS status. In some cases, L2 cache memory error
is seen when that register write is flushed whereas usb phy
clock is turned off.
CRs-Fixed: 990963
Change-Id: Iebe8cb4034721e76fa5ea63e33304b9dc0243797
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Extended compat ID descriptor contains fixed-length header section and
one or more function section. Function section contains five fields as:
bFirstInterfaceNumber, Reserved1, compatibleID, subCompatibleID and
Reserved2. Specification suggests that Reserved1 needs to be set as 0x1
but f_fs driver fails processing descriptors if Reserved1 field is 0x1.
This results into USB enumeration issue due to incomplete descriptors.
This issue is seen with newer adbd which is passing extended compat ID
descriptors.
CRs-Fixed: 994161
Change-Id: Id18261d76edd859ef078f4510dd82b8a6c1ca4bd
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Currently used USB QMP PHY register address space size is 0x45c which is
used by Linux USB QMP PHY driver to memory mapped the region. Some of
QMP PHY registers' read/write offset is above this size. Hence increase
USB QMP PHY register address space size to 0x7a8 to memory map complete
USB QMP PHY related register address space.
CRs-Fixed: 992231
Change-Id: I2a861c6a0d34d75aaad508b182c4007b6b448c2e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Extend the IOCTL argument to support a vmid parameter for describing
which secure pool the prefetch is for. Also allow multiple different
memory sizes to be given to more accurately describe the future
allocations.
Change-Id: I8a91ef2f8ecf2075c18c963b4c82ca0e97ea770d
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
The previous implementation of moving pages to the uncached pool before
freeing them is unnecessarily complex.
Follow the same methodology as ion_page_pool_shrink().
Change-Id: Ic69947c18b5899e5ca75b7e0039e4e2869a5dfa6
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
After creating all secure pools successfully, i == VMID_LAST.
If ion_system_heap_create_pools(), the error path will attempt to
destroy all secure pools, starting from i.
But this is one past the end of the array.
struct ion_page_pool **secure_pools[VMID_LAST];
Change-Id: Id97ab40a1dc0885f476f6e25cdd324f5ee3dcf04
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Optimize the Ion System Secure Heap by adding per VMID
based page pooling. The secure/assigned pages are pooled.
This essentially uses the same pooling functionality as
the system heap, but adds the VMID component to each pool.
Change-Id: Ib65b3f490ab1bb299b57227edba88b876924ff2b
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
The MSM ion implementation moved the dma_sync call to
ion_system_heap_allocate()
It was inadvertently added back to
ion_page_pool_alloc_pages() by
commit cb22ca6421
("ion: add snapshot of ion support for MSM")
Change-Id: I61029996e59c754b37f45543c4263a100b427867
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
commit cb22ca6421
("ion: add snapshot of ion support for MSM")
mistakenly changed the behavior of ion_system_heap_shrink.
Restore the upstream behavior.
Change-Id: I5c989eefb7196925b11fc6519fb22628994aed30
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
The meaning of the flag "cached = ion_buffer_cached(buffer)" is different
between the msm and upstream ion implementation.
Upstream:
cached means get memory from the ion_page_pool vs. buddy allocator
MSM:
cached means get memory from the cached ion_page_pool vs. uncached
ion_page_pool
if the new flag ION_FLAG_POOL_FORCE_ALLOC == true, then use the buddy
allocator.
In upstream commit ecd32842283c64b14243be9b20b60f351aea1b5d
("ion: Handle the memory mapping correctly on x86")
pages allocated from the ion page pool may have special page table
attributes. These attributes must be unset before the page is returned
to the buddy system.
This issue was introduced by an incorrect cherry-pick of the above
change.
Change-Id: Ia9339e78a4fa3f4734b6c75bb35d226f293dafb5
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
PCIe Advanced Error Reporting is currently enabled
by default with no way of disabling it. AER is not
always ideal to have enabled as it may flood PCIe
IPC logs. Thus, this change provides an option to
enable and disable AER from debugfs.
Change-Id: Ic5b90ad47b4d97ad492745c1f57e1ab85236772a
Signed-off-by: Tony Truong <truong@codeaurora.org>
