If request has to be requeued (due to any DCMD commmand pending or cmdq
being halted) and if we change the task status to interruptible before
going to sleep then thread may not wakeup again. Note that
blk_requeue_request() doesn't trigger ->request_fn() again to wakeup
the thread.
Fix this issue by making cmdq thread wait for the completion of DCMD
or until the cmdq is unhalted. This change also simplifies the
cmdq thread function.
Change-Id: Iebffc993241e5fadb2962fedc44576566dc66e9c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The SDHC spec allows to force raise errors that is useful for
debugging error handler routines. Add debugfs entry force_error
to trigger host errors from userspace. Check SDHCI_SET_INT_ERROR
register for error bitmask info.
Usage: echo 0x1 > /sys/kernel/debug/mmcX/force_error
X - denotes the slot id
Change-Id: I9f67442a79b2645cbdc3020d1a10c0b32840ce32
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
To trigger queue status command after sending dcmd, we need
to set bit 31 of CQ_VENDOR_CFG register. But the current code
incorrectly sets bit 31 of CQCTL register.
Change-Id: Ic5b914cf6a5237ac51b2104453caba2c49c1efbc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
With newer mmc drivers, max_discard_to has been remvoed from the sdhci
driver. So instead of incorrectly using max_busy_timeout for
calculating max_discard to be used by mmc queue, use the mmc cap to
indicate that the max discard should be used for msm sdhci driver.
Change-Id: I424cd0a5ee9ffd7199be58a5a091984c5fcda52f
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
max_busy_timeout is used to decide whether R1B response should be used or a
R1 response should be used. This is also used to decide what the discard
size of mmc queue (registered with block layer) can be set to. In order to
keep both the features in place, this change will allow for hosts to
specify a larger discard size while still specifying max_busy_timeout.
Change-Id: I1e607329c4377897a7cb4086db02cbc150bd02b7
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
"downdifferential" parameter of devfreq's simple ondemand governor supposed
to report expected difference between upthreshold and downthreshold value.
In other words, downdifferential = upthreshold - downthreshold. But
currently downdifferential is set to same as downthreshold, this change
fixes this issue.
Change-Id: Ic2e762d192f1fed8f94d4d2579d6a4b5d4c2c8b5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The controller triggers an ADMA error when ADMA engine is configured
and used in 32-bit mode. This is because the current code always
writes 64-bit address to 32-bit address field of a transfer
descriptor (bits [63:32]). This corrupts the first 32-bit value
of the next transfer descriptor.
Below scenario describes how ADMA error can happen -
1. Req#1 - uses slot 1, prepares it's descriptors, queues to the controller
2. Req#2 - uses slot 0, prepares max descriptors (cq_host->mmc->max_segs).
3. Req#1 gets ADMA error from the controller.
At step 2, when it prepares the last transfer descriptor (max_segs), it
overwrites the 32-bit address field with a 64-bit address and thus corrupts
the first entry of slot 1 transfer descriptor.
Change-Id: I3eb2dbb40c76ec77626f647d6ec24df4a0858fcb
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add sysfs entries to allow getting the current status of
PM QoS voting and enable or disable voting.
Change-Id: If5b8e4b155090343112916c9c57a766bb2104e10
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Starting from MCI_VERSION 4.2.0 use a different offset for the following
registers:
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_n
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_WRAPAROUND
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_OVERLAP
In addition, move dump debug ram functionality to the MSM specific file.
Change-Id: I3b0f5101150de9f2c190ce69b306bd151cbb65ae
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
IOCTL and RPMB commands can be issued while the device is busy
with background Operations handling.
Stop the device BKOPs before handling the RPMB / IOCTL command.
Change-Id: I088f74c77026ccd901276e1214e4466ac7815bf1
Signed-off-by: Maya Erez <merez@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
DCMD requests don't have data, check for the data pointer before
accessing it to prevent null pointer dereference in case of DCMD
timeout err. Also signal a completion event for non flush requests
like discard that wait for the completion of DCMD request.
Change-Id: Ia71a5f1e278a039ba22f6ac42614d9ae79dba7e9
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Read the firmware version from ext_csd register and print it
for debugging purpose.
Change-Id: I4c1fefd5bff753915c9858fb35c958335986c778
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts and
compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Dump crypto related register information during error for
debugging purpose.
Change-Id: I8976e8c0b5e9bda910634464202578dbacd7666e
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Clock scaling commands are not allowed to be sent when the device
performs manual BKOPS.
In case the device is busy with manual BKOPS, skip the clock
scaling and allow the device to continue the BKOPS.
Clock scaling will be invoked again later by dev freq.
Change-Id: I78b505326d245b1ddcd9d6f1cdd4294850889d45
Signed-off-by: Maya Erez <merez@codeaurora.org>
In case there are no pending requests, runtime idle API can be
invoked and start manual BKOPS.
We need to check if manual BKOPS is enabled on the device and stop
it before serving new incoming requests in CQ mode.
Change-Id: I870eff40ea9fa91eedb4c0d2600c32d8534a3868
Signed-off-by: Maya Erez <merez@codeaurora.org>
This change adds the ability to partially initialize
the MMC card by using card Sleep/Awake sequence (CMD5).
Card will be sent to Sleep state during runtime/system suspend
and will be woken up during runtime/system resume.
By using this sequence the card doesn't need full initialization
which gives time reduction in system/runtime resume path.
Change-Id: Id8dadf03ef4226f7c4675fadbacac7bb15c0289e
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts & compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for legacy
eMMC.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I5d2b71fc4eabfa5060f343634fbc7363f2ee1344
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for command queueing.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I8a20653eeb6348d5b442c846708d92c8fb64a8e9
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
When encryption/decryption is enabled in CQ mode, the
legacy commands that are sent in HALT state will use
different slot other than slot 0 for crypto configuration
information. The slot that is selected depends on the last
slot that was used when it is in CQ mode. This is causing
the data of legacy commands to be encrypted/decrypted based
on the wrong slot usage for crypto config details. Hence,
clear the crypto configuration of the slot used in CQ mode
whenever it gets completed.
Change-Id: I6817de46d895b61f410dd732be57ba60efb58fb2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
There can be a race condition between runtime idle and incoming
requests. In such a race condition, we can send requests
while the queue is halted.
Claiming the host at the beginning of runtime idle will prevent
such a case.
Change-Id: I8e55f0798543b2de44b37da13f7770889e6fbe5f
Signed-off-by: Maya Erez <merez@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add the necessary device tree properties and parsing in the driver
to support PM QoS voting for IRQ and CPU groups for CMDQ / legacy modes.
Change-Id: I1a94978ca66823d2ce78ee230cf36b4ebb72e6d8
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
pm_qos is causing race conditions in CQ mode with
power management. Removing the feature in order to
allow power management.
Change-Id: I340cd784829f389f18df6bff664337aca0f3c867
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Any CMD/DAT errors raised using the error interrupt status in
CMDQ mode also needs to be cleared. If this is not cleared,
any error in supported CMDQ CMD's like CMD 44/45/46/47/48 will
cause an interrupt storm.
Change-Id: Ie725bbf1c859a2dc91b64274e05e71328dfeb1b2
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This patch adds checks in msm host driver to check if card
also supports enhanced strobe before changing strobe specific
host configuration.
Change-Id: Iab4833e80600c4ad89b16c76b52e917f885eea0e
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Should check if mmc_card supports strobe before calling
enhanced strobe host ops. This also adds a macro for use
by LLD to know if card supports strobe
Change-Id: Id79098ff66bd36be2496b86bf71556204aca7fe3
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
When encryption/decryption is enabled in CQ mode, the
legacy commands that are sent in HALT state will use
different slot other than slot 0 for crypto configuration
information. The slot that is selected depends on the last
slot that was used when it is in CQ mode. This is causing
the data of legacy commands to be encrypted/decrypted based
on the wrong slot usage for crypto config details. Hence,
clear the crypto configuration of the slot used in CQ mode
whenever it gets completed.
Change-Id: If573de5025054a10de1dde544aa79022016f65fd
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The mmc_queue_req will be present only if the request is issued
to the LLD. The request could be fetched from block layer queue
but could be waiting to be issued (for e.g. clock scaling is
waiting for an empty cmdq queue). Evaluate such cases and reset
the timer to give LLD more time.
Change-Id: Ic5818f5c2b8356bda9b1612d78b65e07dad011d7
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Update the error code to ENODEV if eMMC is not the boot device.
Change-Id: Ide0863a5aa64f9990d39095de6f6b13f752a6b3e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Use the tag id of the error'd request and don't reset it to zero;
to handle the error'd request appropriately.
Change-Id: I0f5eac47197fa7b59208d0a61776d4ba186aa3dc
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The power on reset value of DDR_CONFIG register was fixed in
controller revision (major - 0x1 and minor > 0x49) to address
the default rclk delay value after characterization. The register
offset for this register was also changed starting from this
revision. Make necessary changes to account for this.
Change-Id: I4e4a87aebd24e5669b03a914c6e0f4b469f5ec7b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This change adds use of devfreq suspend/resume API.
In the current version of the code, devfreq is fully brought
up/down on each runtime resume/suspend which causes
statistics loss and is time consuming.
This change addresses the above by adding support for
devfreq suspend/resume to be called on each system
suspend/resume, runtime suspend/resume, power restore.
Change-Id: Id209826fb9499084ae96c7d3a47e4032326f61e9
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
In case of a crypto error during request submission clear the
host mrq structure in preparation for the next request and
dump the current register state for further debugging.
Change-Id: I2eeda8589ca4c83bbb4a1b372e9363224bbfb680
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
For any cmd we have a DAT line timeouts which we set in TIMEOUT_CONTROL
register of sdhci. For commands with busy response (R1B), cmd is followed
by a busy period exercised by card, by pulling DAT0 line low
(in case of CMD5). Here host controller detects this busy period and
waits for either busy period to finish or timeout to happen based on
value set in SDHCI_TIMEOUT_CONTROL register.
Thus for R1B commands, host controller(sdhci) is capable of sending
two interrupts. 1st is the CMD response(0th bit - Command complete
of Normal Interrupt Status register ) and 2nd is when the busy period has
ended(1st bit - Transfer Complete bit of Normal Interrupt Status register).
If MMC_CAP_WAIT_WHILE_BUSY is not enabled by the host controller driver
then core layer explictely waits for fixed amount time specified by
s_a_timeout parameter which is generally very high when compared to
amount of time card keeps the DAT0 line low.
As sdhci-msm is capable of detecting this busy period, set
MMC_CAP_WAIT_WHILE_BUSY capability in the host controller driver
to avoid redundant wait period.
On 8952 this saves us ~110ms during mmc suspend.
Change-Id: Ibb3a70575a06a5ffd1ccc3adaa96dfb3c3e22e3a
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
We should keep either one of CDR_EN or CDR_EXT_EN enabled.
So correct this logic in toggle CDR function.
CRs-fixed: 759398
Change-Id: Ic137ae2a28e912ab131644ff9d81e41f4256dd05
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
During tuning the status command CMD13 needs to be sent to the
card to know the card's state upon any failure to tuning command.
Change-Id: Iaefc80305d101bd72ff22f792b1967379507a739
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Currently we enable CDR for every read command including
for tuning procedure which is not correct (as CDR if
enabled might correct the phase during tuning and we
wont be able to detect the correct phase during tuning).
So, disable CDR for read tuning commands.
CRs-fixed: 759398
Change-Id: I051b6e3b204dde22cdc973759c3e32d0a81c369a
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
During platform driver probe we call mmc_start_host in sdhci_add_host,
which could start the mmc_rescan work immediately and trigger a runtime
suspend. This creates a race condition where the clocks could be turned off
even before the probe has completed leading to unclocked register access.
CRs-Fixed: 770843
Change-Id: I77ae36f805e496d56ed96db3ccaa83f2c37c926c
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some controllers may not have any LED control to indicate
its status. Use this quirk for such controllers to avoid
registering any LED device with LED class and also to
avoid exposing sysfs nodes which doesn't actually control
any LED.
Change-Id: I7e8f1b8d2d735685ede87df4bb7fb32ad0a10246
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHCI reset for data is getting stuck on some of sdhci-msm
controllers. The SDHCI reset usually waits for any pending transfers
on the bus before proceeding with the controller reset. But in the
failure cases, the data transfer seems to be stuck on the bus and
thus preventing the controller from being reset. The workaround is
to force the controller to be reset under such scenarios. This seems
to be helping the controller to return back to good state at least
for the next commands following the failure.
This issue is found on SDCC5 controller of 8916/8939 and 8992 chipsets.
Hence, enable the quirk SDHCI_QUIRK2_USE_RESET_WORKAROUND only on those
controllers.
Change-Id: Id49009736beb410ccb2535d614786a7c48098f85
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
The SDHCI reset for data is getting stuck on some of sdhci-msm
controllers. The SDHCI reset usually waits for any pending transfers
on the bus before proceeding with the controller reset. But in the
failure cases, the data transfer seems to be stuck on the bus and
thus preventing the controller from being reset. The workaround is
to force the controller to be reset under such scenarios.
This seems to be helping the controller to return back to good state
at least for the next commands following the failure.
Change-Id: I487bdf3bd4afb18e69afa778aa38c3574d69e2f7
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHCI reset for data is getting stuck with the default
MID configuration which uses descriptor requests with MID=0
and data requests with MID=1. This enables interleaving
between MID and is causing reset to be stuck somewhere in the
path DDR<->NOC<->SDHC on few chipsets. Enable one MID mode
as a workaround to this problem which is observed on SDCC5
controller of 8916/8939 and 8992 chipsets.
Change-Id: I12343b35d45774668b7e823ccaa067813fcea4cf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Runtime pm get/put calls need to be called in pairs. Fix the
unpaired call of runtime pm put after input validation.
Change-Id: Ice2ba1e4d17ffde48b2f4d59801bb962f2e9aae7
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In case card detect IRQ is triggered before mmc_add_host(), then
there could be a potential race between mmc_power_off() which gets
called frommmc_rescan() of card detect IRQ handler and
mmc_start_host() which gets called from mmc_add_host(). This may
turn off the clocks while mmc_start_host() is still running and thus
may result in an un-clocked register access.
Change-Id: I90ff99fb8e018b00600bf18197a2bcaf83ff1bc4
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts, removed
2nd pair of mmc_claim_host/mmc_remove_host calls from mmc_start_host]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SANITIZE is an operation performed by the storage device and its purpose
is to delete its unmap memory regions.
This change adds support for the SANITIZE capability.
Change-Id: I58b647fb576c694aaa16c1e827d0784d4a5b4456
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
pm qos is currently causing race conditions with runtime pm when
in cmdq mode. Disable this till it is addressed as part of the
pm qos redesign.
Change-Id: I32d04100bbf31995a249188eace164c8761e9141
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Change the rclk delay value to 0.9ns since testing shows
that the valid window may vary for different platforms and the
default value (1.25ns) might fall outside the valid window.
CRs-Fixed: 766702
Change-Id: I6e3522c2764047a773e028078b63e6e94e230d41
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spurious power IRQ which results in system instability.
Change-Id: I1c4f27e131992ef036ebe64fbb2c52613ba396cc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
If request has to be requeued due to cmdq being halted and if we change
the task status to interruptible before going to sleep then cmdq thread
may not wakeup again. Note that blk_requeue_request() doesn't trigger
->request_fn() again to wakeup the cmdq thread.
Fix this issue by kicking the queue once cmdq state machine is unhalted.
Change-Id: Icbfb3b6560285fa0a0ce7e83eee66b651d4594a0
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This change makes sure we will do deferred scaling only
from data path and not for other requests such as mmc_switch.
Change-Id: I52142d7a0262ca8927c7c1c509235ead676aac97
Signed-off-by: Talel Shenhar <tatias@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Clock scaling logic relies on active data request tracking variable to
start/stop counting the bus busy period and we are also crashing the
system if this tracking variable shows that new request tag is already
in use. Set/Clear logic of this tracking variable is done only if
clock scaling is enabled but consider following sequence of events:
1. Clock scaling is enabled
2. New request comes in which sets the appropriate tag in tracking
variable.
3. Clock scaling gets disabled (for some reason) before the request
completion.
4. Request gets completed but it doesn't clear the corresponding tag
in tracking variable.
5. Clock scaling gets re-enabled.
6. New request is issued with the same tag which was never cleared from
tracking variable hence we would hit the BUG_ON and system will crash.
Fix this issue by doing set/clear of tracking variable irrespective of
clock scaling state.
Change-Id: Idffd1247ec1275e782e1ad9eb91faa81bc3ba347
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
