Userspace may already know that the checksum validation is already
completed prior to being passed to the TUN interface. As a result,
computing checksum again in network stack may be a redundant
operation.
Add support to read this information from the TUN header flags
to skip checksum validation for these packets only.
This is useful in cases where the packet checksum was computed by
hardware for IPv4 / IPv6 TCP / UDP packets. Since the packet
intergrity was already verified for packets over the wire, subsequent
validation within the network stack is redundant work.
Change-Id: I18ee3408c05910207b205d6205f282e6f3599156
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
A low cost method of determining GRO statistics is required. This
change introduces a new counter which tracks whenever GRO coalesces
ingress packets. The counter is per-CPU and exposed in
/proc/net/softnet_stat as the last column of data. No user space
impact is expected as a result of this change. However, this change
should be reverted if legacy tools have problems with the new column
in softnet_stat.
Change-Id: I05965c0cb150947935d5977884cc4d583b37131d
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Reserved ports may have some special use cases which are not suitable
for use by general userspace applications. Currently, ports specified
in ip_local_reserved_ports will not be returned only in case of
automatic port assignment.
Add a boolean sysctl flag 'reserved_port_bind'. Default value is 1
which preserves the existing behavior. Setting the value to 0 will
prevent userspace applications from binding to these ports even when
they are explicitly requested.
BUG=20663075
Change-Id: Ib1071ca5bd437cd3c4f71b56147e4858f3b9ebec
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Modify the printout functions for IPv4-TCP, IPv4-UDP, IPv6-TCP, IPv6-UDP,
such that the state for the socket is printed as state = state | 0x80.
The actual socket state is unmodified. This change is required for the
user space to determine whether a socket is a transparent socket, and
to determine if the socket holder intends to consume packets locally
or to forward them to an external processor.
Change-Id: I2ca403b4c2c74e7ddcdbda53e4ba43613bae9c42
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Cloned packets arriving in ingress path can cause issues with GRO
since the skb shared info is garbled.
Warn once if a cloned packet is queued up to the network stack.
CRs-Fixed: 823275
Change-Id: I049f04f39b3d1338838560e08c93a973de427fc0
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
UDP IPv4 encapsulation sockets will have their state printed as 0xF0
binary ORed with the actual state such that they can be distinguished
from regular UDP sockets in /proc/net/udp.
CRs-Fixed: 821341
Change-Id: I240ab1526a4280e5e996d9577a904581684fc84a
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Too many socket events are generated by netlink socket. Filtering out
unwanted socket events.
Change-Id: I3a4d7e14843cf72d6af2d948113b27928ed01adb
Acked-by: Krishnan Ramachandran <kramacha@qti.qualcomm.com>
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
Ensure that BIND and LISTEN syscalls do fput_light AFTER sockev notifier
callback has returned. Also, increase refcount on sock->sk (if available)
before invoking the notifier callback. Prevent crash due to use-after-free.
[<c0891d5c>] (sockev_client_cb+0xfc/0x1e4) from [<c0a273a4>] (notifier_cal
[<c0a273a4>] (notifier_call_chain+0x44/0x84) from [<c01422cc>] (__blocking
[<c01422cc>] (__blocking_notifier_call_chain+0x48/0x60) from [<c01422fc>]
[<c01422fc>] (blocking_notifier_call_chain+0x18/0x20) from [<c0865968>] (S
[<c0865968>] (SyS_bind+0xb0/0xe8) from [<c0105ba0>] (ret_fast_syscall+0x0/
CRs-Fixed: 787283
Change-Id: I2de65929b22c58637692cf582b6b46b11713494e
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
Added module which subscribes to socket notifier events. Notifier events
are then converted to a multicast netlink message for user space
applications to consume.
CRs-Fixed: 626021
Change-Id: Id5c6808d972b69f5f065d7fba9094e75c6ad0b2c
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Allows other areas in the kernel to register notifier callbacks which
get invoked whenever something performs an administrative action on a
socket. This patch adds hooks in socket(), bind(), listen(), accept(),
shutdown().
CRs-Fixed: 626021
Change-Id: I4ae99cb2206d7c4eddba69757335c18d10143045
Signed-off-by: Harout Hedeshian <harouth@codeaurora.org>
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
The current PHY sequence is not fully compatible with the
QSERDES PHY found on mdmcalifornium. Thus, add the new
sequence and other changes to support PCIe QSERDES PHY
on mdmcalifornium.
Change-Id: I5a5d0b115651a159612e17debf0d25d6f88dbee8
Signed-off-by: Tony Truong <truong@codeaurora.org>
Currently, PCIe bus driver on mdmcalifornium does not
have support for ARM32. Thus, add the necessary changes
to support ARM32 for PCIe on mdmcalifornium.
Change-Id: I6c72debd9ea65b7abb70ce4d5568c972ba786c11
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all targets will have a dedicated line for each PCIe
interrupt. On these targets, some PCIe interrupts will be
aggregated into one line. Thus, add support to handle
aggregated interrupts.
Change-Id: I4f5be73718d4a4ae8a3de142579f24a7113fe086
Signed-off-by: Tony Truong <truong@codeaurora.org>
Based on si learning, new PCIe PHY settings improve the overall
stability of PCIe PHY on MSM8996 v3 and on v4. Thus, update the
PCIe PHY sequence for MSM8996 v3 and v4.
Change-Id: Ia1ab0af4c4dcf483d3b3dc05b7b13003de788f40
Signed-off-by: Tony Truong <truong@codeaurora.org>
The counter for the number of active root complexes
determines when PCIe common PHY should be powered on/off.
To avoid conflicts and a stale counter, add locks to protect
the access to PCIe common PHY.
Change-Id: I18ec54e52e804eb132f9c5c0270455dbc9187151
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all endpoints require PCIe WAKE support.
Therefore make PCIe WAKE GPIO optional.
Change-Id: Ifc5a84204cde42881a127b4715727c290ee24450
Signed-off-by: Tony Truong <truong@codeaurora.org>
In addition to having outputs to kernel log, PCIe
debugfs messages should also be captured in IPC logging.
Therefore, add a new IPC logging label and update the
existing calls to do so.
Change-Id: I2ab6a6549575c4e2de2f1ef0756328f4b6f6a178
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe bus driver can now use devicetree to help distingush
which PCIe QMP PHY version is being used. This will allow
PCIe bus driver to choose the correct PCIe PHY sequence.
Change-Id: I74c67431b75292bb1db3e4b97d89d69de9b6f11b
Signed-off-by: Tony Truong <truong@codeaurora.org>
Current PMIC API call to disable CX rail does not remove
PCIe power vote. Add another API call to successfully
remove vote when releasing this resource.
Change-Id: I5203203e10e8e690745768c241e92d298b87cc4b
Signed-off-by: Tony Truong <truong@codeaurora.org>
To improve PCIe PHY stability, add a delay between
the write of power down and sw reset register on
MSM8996.
Change-Id: If09390bff59e0922cb891c7bac823c11361fca83
Signed-off-by: Tony Truong <truong@codeaurora.org>
In order for PCIe to reliabily work in SVS mode,
the PCIe PHY RX clock needs to be slowed.
Change-Id: Ic6edf487011ef4ac71d486210b1f6176e2142551
Signed-off-by: Tony Truong <truong@codeaurora.org>
Increase the wakeup delay time for PCIe aux clock on MSM8996
to improve PCIe stability when waking up.
Change-Id: I2909e80a2c79b4f17ca39c39d899de08b67d4120
Signed-off-by: Tony Truong <truong@codeaurora.org>
Each PCIe client requires different CX power levels
to maintain functionality. This change gives each
PCIe root complex the ability to vote for CX power
levels.
Change-Id: If027c79220253a60837c3d52202fb5ec4cc3451e
Signed-off-by: Tony Truong <truong@codeaurora.org>
New QMP PHY sequence for 1MHz aux clk for PCIe
on MSM8996. Therefore, update the PCIe PHY
sequence.
Change-Id: I2b3746cc9d6ab6b491fa7404ae54fefbf36df905
Signed-off-by: Tony Truong <truong@codeaurora.org>
There are unnecessary cleanup code which alters the descriptor
of a Synposys MSI IRQ and this causes the IRQ to be unusable
afterwards. Remove the unnecessary cleanup code for Synopsys
MSI so that the IRQ will remain functional.
Change-Id: I87221f9a59d014df21af251277866c511c5375eb
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for 3.18 kernel. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Signed-off-by: Tony Truong <truong@codeaurora.org>
Increase the Ipeak request for each PCIe LDO based
on updated settings.
Change-Id: Ie3af6462dac68252b339595e350e393079a89bb9
Signed-off-by: Tony Truong <truong@codeaurora.org>
SMMU requires PCIe to provide a SID for each of its endpoint
so that the endpoint can successful transaction on the bus.
This change adds the support for PCIe bus driver to calculate
a SID for its endpoint and give it to the SMMU driver.
Change-Id: I52099bbfed0a38c75b0277b0f58f45f6e6559695
Signed-off-by: Tony Truong <truong@codeaurora.org>
In the case where the Root Complex fails to retrive a valid
index, the exit code fails to handle this correctly. This
change corrects the way the exit code handles invalid root
complex indexes.
Change-Id: Ie832fec1be2b05dea05b8917348a1c08cdc1d681
Signed-off-by: Tony Truong <truong@codeaurora.org>
Some EP requires additional GPIO to be enabled for link training.
Add the support in PCIe Bus Driver to manage this GPIO.
Change-Id: I837edae478779fdaf3e94c70a0a031f9d0580a77
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe on some targets require the iommus device tree entry.
Therefore, add this device tree entry to the PCIe
documentation.
Change-Id: Iec6c4cfcd5e51d6aa1259bb826fe60d131072170
Signed-off-by: Tony Truong <truong@codeaurora.org>
There are new PCIe PHY settings that have been updated
to improve performance and stablilty. Therefore, update
the PCIe PHY sequence on MSM8996.
Change-Id: If321471c51ff6a91595b68bd2cae08c8c043d6bb
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support more accurate benchmarks, add entry and exit logs
for PCIe functions.
Change-Id: I49f27263722adfaa8ae3973f242faa6a589d3358
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support PCIe MSI on 3.14 kernel, the client's host
driver must use the QGIC IRQ number to request/enable
the interrupt while the client's firmware must use
the SPI number to trigger the interrupt. Therefore,
add this logic in PCIe bus driver to support MSI
interrupts on 3.14 kernel.
Change-Id: I165022281c9e795be8c5e2e4a4faa34d4c004a45
Signed-off-by: Tony Truong <truong@codeaurora.org>
After writing to a PCIe PHY debug register, the wrong
PCIe PHY status register is being read back. This change
corrects the PCIe PHY status register that is read back.
Change-Id: If360aa6f9b4530e4c07acfcc1af684c6d7ecc234
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for thulium. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c
Signed-off-by: Tony Truong <truong@codeaurora.org>
When searching for the endpoint's capabilities register,
check that the value from the register read is valid.
Change-Id: Ia64de3c75618ca0a51aa4588ac97f2fcb26d8829
Signed-off-by: Tony Truong <truong@codeaurora.org>
When reading shadow registers, the wrong value is being
recovered for root complex L1 register. Currently,
the value being recovered is a shadow of the endpoint's
L1 register. This change will recover the correct shadow
value for RC L1 register.
Change-Id: I82b1810ef8761de90b350743cdd9b24a74efb62f
Signed-off-by: Tony Truong <truong@codeaurora.org>
There is an extra identical call made to check if aux clk
is supported base from PCIe device tree node. There is no
need to do this check twice; therefore, remove the duplicate
call.
Change-Id: If705e98e637287969d68ea2241e62447aa505eb0
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all the testcases for debugfs needs the calculated offset
of an endpoint's capability register. Therefore, only calculate
the offset of an endpoint's capanility register if that testcase
needs it.
Change-Id: Iffddcea682d8c9344f51a04b57f60ba906b01dc6
Signed-off-by: Tony Truong <truong@codeaurora.org>
When the clients want to enable common clock for the
endpoint, also enable it for the root complex.
Change-Id: I55d5a69be0746a745b073051452d45a38d0a4e65
Signed-off-by: Tony Truong <truong@codeaurora.org>
FSM9010 requires a different PHY sequence. Therefore,
this change adds the PCIe PHY support for FSM9010.
Change-Id: Ic98860d3ac1f7b644b76064032f399f070fc9b47
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the clock power management for the
endpoint.
Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
