PM_QOS will put the interrupt where it wants to and we're okay
with that.
Change-Id: Ic0dedbad5294d51a55125a0021f7dcc3b185de02
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add LMH DCVSh mitigation support for kernel thermal driver for sdm630.
It enables KTM to request frequency mitigation to LMH DCVSh hardware
block.
Change-Id: Ia546f004416dff2da7c6560b8e582eac563d3f8e
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Enable LMH DCVSh driver for sdm630. It adds information about
the interrupt generated by the LMH DCVSh block for sdm630.
Change-Id: I16a5f9f0737e64b4ed0e39e0624afb64fbf623e7
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Update LPM parameters latency, ss power, time overhead and
energy-overhead with the values measured at minimum frequency.
Change-Id: Id5fc176a02978c54e4cb4faec4dffca83a7cbea5
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Some drivers (e.g. OLEDB) would need to know about LAB_VREG_OK
status from the LABIBB module. Hence, add support for the
notifier callback so that required drivers can be notified about
LAB_VREG_OK status.
Change-Id: Ib60c94c7557ee6ffb7595dee5bd268bb76faaf6e
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm8998 needs an additional 5V pin to be
enabled to power the HPD circuit. This change
enables the support for this pin.
Change-Id: I42f91265ce56ff5505e3d9c2382858fe6c1be52b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
When HPD is enabled in DTSI for HDMI display, driver needs to poll
the HPD status change and report event back to user space.
Change-Id: I6dd2f3078875698ff8cfd7bdb7cfd662e85eec9b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Sde io util provides apis for clock management,
regulator management, gpio, register read/write,
etc. This enables the APIs callers to manage
the hardware resources. This patch adds the
io util API support to msm drm driver.
Change-Id: I3b61d42d15659eccde4303e0f68615620b344075
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Sometimes the HDMI is treated as non-pluggable display in auto
use cases. Add support to configure it through dtsi file, and
also provide timing parameters for the customized modes through
dtsi.
Change-Id: I2326b6c43cb7e6361be1f14d25f0e2e493c94177
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Include SDE DTSI for MSM8998 chipset. This
ensures that boards and targets using SDE driver
will use the new DTSI.
Change-Id: I9dfe8c48efbee5cb4f85fe684a06a2023abfda53
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
APQ8098 mediabox shall use the new SDE driver.
Disable the mdss_mdp device node on APQ8098 mediabox to avoid
duplicate probes.
Also make HDMI as the primary display for APQ8098 mediabox.
Change-Id: I9bea09473fccf2bf3048f0e0428b94bb16be3eda
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Rename mdss_mdp to sde_kms in the device tree to reflect the
new display DRM driver terminology and add support for HDMI TX
device node
Change-Id: Ide5dc6a5939945a3e993eca650c66a56f3955140
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Updating min frequency for memlat voting from 633MHz to
902MHz to avoid intermediate DDR frequency switching on
SDM660 target.
Change-Id: Ic68cbd15757bdc5ee1dbaef1d850a699c614837c
Signed-off-by: Nikhil Kumar Kansal <nkansal@codeaurora.org>
Add MDSS reg bus scale properties for sdm660 and sdm630.
These votes are required for faster reg access especially
in cases like histogram/gamut where we read large number of
registers.
Change-Id: Ia7aac81216b4138b583b37a938643eb950b5dcfc
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
In existing implementation elf region was being clearead before memory
access to firmware region assigned to HLOS. So to avoid it using
separate function which will be called only when HLOS is the owner.
Change-Id: I8bb22e4dbe3e1f898678d0c0f6e60268b88fc150
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Update the fuse corners supported for APC0/1 CPR instances of sdm630
as per the new fusing scheme.
Update speed-bin 2 frequency for TURBO_L1 to match the clock node
mapping.
Update the ceiling voltage limits for interpolated voltage corners
to that of their next fused voltage corner.
CRs-Fixed: 2008764
Change-Id: Iff104afa9750ba4be131cf142fc9eec01910678c
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add INT3_MI2S interface support for source tracking as INT3_MI2S_TX
is used for capture in the internal codec for SDM660.
CRs-fixed: 2007623
Change-Id: If0c72ad0942fc56b2778b831de019052c8fe31c0
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Timeout errors can occur because of execution error in device during
execution of last command. For errors encountered while executing
commands in card, like cmd46 or 47, the card will stop execution and
wait for the next command from controller to return error information.
If controller sends no command, then a timeout error will occur. To
retrieve the error information in card, send status command must be
sent. In case a non-timeout error like RED error is detected, there
is no need to send CMD13 to card as the error information is already
present in the Resp Arg register.
Change-Id: I6ac0d3db834a3d5a6c67ee08d6232240c35714ff
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Update the number of fuse corners used for APC0 and APC1 CPR
instances of sdm630 as per the new fusing scheme.
CRs-Fixed: 2008764
Change-Id: Icee251c350c102c698c2f60f3189e5aecf2dc7b1
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
When exiting low power modes (M3) do not reset
the DB Mode state if DB mode preserve flag is
set for channel.
CRs-Fixed: 1022868
Change-Id: I6557d28afe9d0ac11b76c683ffba76d7d6ffd377
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
In order to avoid being out of sync between MHI client
and MHI host, host shall not reset the doorbell modes for
hardware channels during MHI_M3 state transition abort.
CRs-Fixed: 1023725
Change-Id: I6c742fc968fd57d71a86039bf1f3f65b1362bc90
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add camera node include rear,aux and front camera to
support the msm8998 QRD HDK device.
Increased the drive strength of mclk clock.
Change-Id: I6c8a3f3c69ca2bc2e3b54b46324525c67d0a2fd3
Signed-off-by: Wei Ding <weiding@codeaurora.org>
To avoid any race conditions between MHI_M2 state
transition and MHI_M3 state transition lock the
entire MHI_M3 transition using xfer_lock.
CRs-Fixed: 972390
Change-Id: I7c2e1b7b3966dc5fb8bf2f91bce734bbc58c6fd7
Signed-off-by: Tony Truong <truong@codeaurora.org>
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
There are instances when MHI channel context read
pointer can be accessed simultaneously by different
CPU cores. To make sure read pointer updates visible
to all cores, add a memory barrier after completion
of MHI ring operation.
CRs-Fixed: 966338
Change-Id: Ifc8c4cd7595fed9049009c42420a665fb170079f
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
