The default configuration for AD config_buffer_mode register is correct
for dual DSI case, but not for single DSI case. This change correctly
set the AD config_buffer_mode for single DSI case.
Change-Id: I8b1b665e027e925d607fda078cc453a5406f85ea
Signed-off-by: Ping Li <pingli@codeaurora.org>
Add new version 5.0 to CSIPHY and CSID documentation
Change-Id: I7295aa6f23b01304c65ff8de08ac115dc53b9803
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
Add documentation file for camera drivers into the 4.4 kernel
tree.
CRs-Fixed: 1001183
Change-Id: I6fe3301673eaba9b8b6fa6c4ad8706fa5e979dd0
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
Use the poll_msec set by the driver that registreed an edac device
to define the poll time for how often the edac_check callback function
should be scheduled.
CRs-fixed: 1001207
Change-Id: I973d7fb966cb9f6f9497510df5de000d4f8ffcba
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
The MMSS SMMU needs a few more clocks for correct operation. Add them.
CRs-Fixed: 1000848
Change-Id: Ica34a3a8b514ca4eebc2fb8081db2b167471cd9b
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
The pll min/max supported voltage has changed from 1.8v to 1.2v,
make the necessary change to reflect that.
CRs-Fixed: 1000754
Change-Id: I4dae3d2471bf3a179e810b5d5520eb26f45e26ba
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enable the UFS and SDHC controllers for cdp and mtp
platform on msmcobalt.
CRs-Fixed: 994739
Change-Id: Ia55c0c59ffad586636a88f42de9fa68656abfe49
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Update the correct clocks and regulators used for UFS.
CRs-Fixed: 994739
Change-Id: Id545c5b8f567e7ccdab1c07af9637848366b49a5
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
On platforms where the power supply for 11AD is external
the wil6210 device can control the rfclk3 clock using a GPIO.
wil6210 driver has to enable the clock during device reset
to guarantee the rfclk3 is on for bootloader activity.
After the wil6210 device is up, the wil6210 driver needs to
leave only the pin clock enabled, to allow the device to
toggle it.
Change-Id: I0f6181d18268f7a2f615155525fbed0f0fe7572a
CRs-Fixed: 986130
Signed-off-by: Maya Erez <merez@codeaurora.org>
Fix type casting in IPv4 and IPV6 driver to avoid compilation
issues for ARCH=um on x86_64.
CRs-Fixed: 996252
Change-Id: Ic3ed8affa2c5bc8fd9b403614f692ab01e1a307a
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Switch the GPU clock to use the gfx_vreg CPR regulator device for
vdd_gpucc-supply. This ensures that the VDD_GFX operating
voltage ends up as low as possible. Also switch the gdsc_gpu_gx
GDSC regulator to use the gfx_vreg regulator for parent-supply.
Add and use a stub regulator for the GFX clock vdd_gpucc-supply
on sim and rumi targets since gfx_vreg may not be usable on these
targets for certain hardware and bootloader combinations.
Change-Id: Ic6536cb90da928ea82d4575922bdf3cb153e5a27
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a VDD_GFX CPR4 controller device which allows consumers to
make voltage corner requests which are then translated to the
minimum possible voltage using the CPR hardware feedback.
Change-Id: Idd5f5380f911b5b5d402b7c19999ce2e300d660d
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a mem-acc-regulator device for the VDD_GFX supply which can
be used to switch the GPU memory arrays into and out of the SVS
voltage usage state.
Change-Id: If2559c619f51bd5a34b7845818ba4c4f8645a975
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Replace the PM8005 S1 stub regulator device with a qpnp-regulator
device. This ensures that consumers physically affect the state
of S1.
Change-Id: I55723cb5a1d49672f243d6911889caa59ec0ee9f
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a dtsi file which specifies the peripherals found in the
PM8005 PMIC chip. Include this new file for msmcobalt boards
since they make use of this chip.
Change-Id: I6620cf1fd5ec4181b7ce79bc97039af954dc324e
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
The subtype register value for PM8005 is 0x18. Add this to the
list of known PMICs.
Change-Id: I5cd316784f1339975a973e63c962fae6cb9db852
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for PMIC FTSMPS 426 type regulators. These have a
4 mV step size and a voltage control scheme consisting of two
8-bit registers defining a 16-bit voltage set point in units of
millivolts.
Change-Id: Id27bf066a014c0a39f47febff2603873050125d9
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for the fuse layout and hardware constraints of the
msmcobalt CPR4 controller which is used to manage the GPU supply
regulator. Also update the cpr3-regulator core driver in order
to support CPR register writing for this device.
Change-Id: I408854a93e820c168551bcfec7d4f87cdbe5d638
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
This is a snapshot of the mem-acc-regulator device tree bindings
documentation file present in the msm-3.18 branch as of
commit 9d555a2ec04c ("regulator: mem-acc: Add support for multi
register configuration").
Change-Id: Iad561ef5bab93f1e82879364639b4a5472e65902
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
The CPR driver on MSMCOBALT needs the gpucc_rbcpr_clk clock in
order to probe and register the gfx_vreg regulator which the
graphics clock driver in-turn is dependent on for registering
the gfx3d clocks.
To break this circular dependency, register the non-gfx clocks
first, let the CPR driver probe, and then register the GPU PLLs
and gfx3d clocks. Also, correct the gfx CRC sequence.
CRs-Fixed: 986619
Change-Id: Id16ad7940e96cc9d5a3127551c8a92b05cfbb181
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Allow the service-locator module to be set via a module
parameter to for another avenue of customization.
CRs-Fixed: 982026
Change-Id: I300b01cc0f130e797734bfb576f2bfedf1075614
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Disable the double bit only flag for edac driver.
CRs-Fixed: 1000784
Change-Id: I54d9e9bf1ecfa0d882574dca7ed3bb7cd53b1ef6
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
PBSS (Personal Basic Service Set) is a new BSS type for DMG
networks. It is similar to infrastructure BSS, having an AP-like
entity called PCP (PBSS Control Point), but it has few differences.
For example, stations inside a PBSS can communicate directly, and
the PCP role can be transferred between stations.
This change adds PBSS support, and has 2 main parts:
1. When starting an AP, add an option to start as a PCP instead.
This is implemented by a new PBSS flag which is passed as part of
the cfg80211_ap_settings structure.
2. When connecting to a BSS, add an option to connect to a PCP
instead of an AP. This is again implemented by a new PBSS flag,
added to the cfg80211_connect_params structure.
Change-Id: Ibfcbeb2df9857fecab4d42f0725d70d2a2fa4b98
Signed-off-by: Lior David <qca_liord@qca.qualcomm.com>
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: eabb03b4a37cc7945ca62453402c74a0622e5a05
Git-repo: https://github.com/kvalo/ath.git
CRs-Fixed: 982931
Signed-off-by: Maya Erez <merez@codeaurora.org>
Add the required ion cma heaps for msmcobalt.
Update the Device Tree with the concerned configuration.
Change-Id: Ie4bd19b0603e856107151972b626c70f9d04a624
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Update the memory map carveouts to be in sync with
the new msmcobalt memory map.
CRs-Fixed: 981975
Change-Id: I5e960ac0553b195e7a69ef596b5fbdcff2064786
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Add SPS module to device tree. SPS (Smart Peripheral System)
enables the support of all BAMs in the system which provide DMA
functionality to various peripherals.
Change-Id: Ib3f0cd293e7e5d09f119c226acdca64c87ca61bd
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add POWER_RESET_QCOM in the perf defconfig.
CRs-Fixed: 1000759
Change-Id: I67181840c8e889ff31111f4fd419edbf5d8d0810
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Certain types of fatal synchronous aborts may be triggered by parity
errors in the L1 or L2 caches. Check whether a parity error occurred and
print out the relevant information.
CRs-Fixed: 1000767
Change-Id: I12b0341148f05a3129e8b1aed3ba322277276360
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
This change add major revision related information for both
QUSB PHY for msm8996.
Change-Id: I68ae8d863a6e438a8d11061db2c75072f4a4e012
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
In new platform, few set of QUSB PHY related operational registers'
offset and usage is changed. This change adds QUSB PHY power up
and PLL lock functionality for QUSB PHY having major revision 2.
Change-Id: Id44c91481d4c184a1991768baf13adad2fae9fb3
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Add Bluetooth device tree for WCN3990 chipset for msm8998.
Change-Id: I45809876336633a496d03e507403944c12f0abb9
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
To support WCN3990 chipset, add control to configure
regulators and clock.
Change-Id: Ibf0e4a0ebd55adaadb6d26b335c3d0a9edbe8845
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
Gpio interrupt target needs to be configured to target
cpu subsystem.
CRs-Fixed: 1000634
Change-Id: I539dc604b150f9f23fda09f343cc5e1d25a6ca47
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
PWM devices can be supported on msmcobalt platform. Enable the
driver support for them.
CRs-Fixed: 999988
Change-Id: I96761cd2bf18bce6ef7795b6686c5da72fe11a89
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
This DT bindings documentation snapshot is taken as of msm-3.18
'commit 0b20839e37187 ("Merge "slim-msm: Synchronize SSR callbacks"")'.
CRs-Fixed: 999988
Change-Id: I59681cf42274f70d5f46b869257a838014d8bf61
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
L2 low power modes between silver and gold cluster has inconsistent
names. Rename both L2 dynamic retention mode as 'dynret' and retention
mode as 'ret' to be consistent.
Change-Id: I18f52fa873b332fb6ad644afc565a84bfed154cc
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Client closing the device immediately after receiving data leaves
the packet arrival wakeup source in active state and block the system
infinitely from entering into suspend state.
Check the state of wakeup source during close operation and release
if it is active.
CRs-Fixed: 989126
Change-Id: I5ad87614edb1307cffaa798f9b393d816dce012a
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
Use GLINK_OPT_INITIAL_XPORT flag to allow the GLINK core to use
the best transport based on available transports.
CRs-Fixed: 994255
Change-Id: I4a0022954d34d52899d5dd357813c4da90717e2e
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
SMD packet nodes are used by user space clients to communicate with remote
subsystems, replace the SMD packet nodes to GLINK packet nodes to remove
the SMD driver dependence.
CRs-Fixed: 994255
Change-Id: Ic0934d795c2c7c20332358a3da603e093f94d980
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
If the local client of the G-Link channel comes up and waits for the
remote client, then it's states are set accordingly. But if the remote
subsystem is restarted as soon as it boots up, then it's states are
not adjusted accordingly. This causes the G-Link channel states to lose
synchronization once the remote client comes up successfully after the
reset.
Adjust the states of the local client if it is waiting for the remote
client and the remote subsystem is reset as soon as it boots up.
CRs-Fixed: 952834
Change-Id: I5fe327ea61eb2d16591861b1246fdca2ecce2b1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Update actuator specific I2C addr_type and data_type
structures. Use the strucutres defined by sensor.
CRs-Fixed: 982082
Change-Id: I77753fd25d5a4256a4a4cdd74518facd63becf25
Signed-off-by: Rajesh Bondugula <rajeshb@codeaurora.org>
When the polling interval is updated, the delayed workqueue is cancelled
and requeued with the new polling interval. However, the bw_hwmon IRQ can
come at the same time and try to stop and restart the delayed work (in the
IRQ thread). This can cause a race where the work might be queued twice or
canceled twice and cause a crash.
Fix this race condition by suspending and resuming the HW monitor when we
are updating the polling interval. This entirely avoids the race because
suspending the HW monitor also avoid the possibility of the IRQ coming
during the polling interval update.
CRs-Fixed: 954082
Change-Id: Ic7baf2a3da4ed8f8a9023617059e22fd81c3ba45
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
In case IPA header has a processing context, header offset is undefined.
This change fixes header log print in case of processing context.
Change-Id: I55e895be945a690a707f6015c09578e31c1de693
CRs-Fixed: 993907
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
