The TYPE for a PMIC chip is always 0x51. There is no need to define it
for each PMIC chip.
Also the SUBTYPE of a PMIC chip doesn't change with versions. Have a
single definition of the SUBTYPE per PMIC chip.
Also, the driver uses integer indexes to get to the pmic name, instead
use the SUBTYPE to index in the pmic names array.
Change-Id: Ie1c43f3db0d4a395307253aad347ad93624a1203
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
An earlier commit 52a3101ed9b61787a49f3b5c298aa9240f4006dd
added a recursive dependency as part of CONFIG_DEBUG_SPINLOCK
lib/Kconfig.debug:585:error: recursive dependency detected!
lib/Kconfig.debug:585:symbol DEBUG_SPINLOCK_BITE_ON_BUG depends on DEBUG_SPINLOCK_PANIC_ON_BUG
lib/Kconfig.debug:593:symbol DEBUG_SPINLOCK_PANIC_ON_BUG depends on DEBUG_SPINLOCK_BITE_ON_BUG
Fix this by adding a choice menu.
Change-Id: I0e50103397bb71dec7056db5148cba988550b860
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Software running in non secure EL1(on arm64) and non secure
supervisor mode(on arm) should use virtual timer for time
stamping. Migrate users to arch_get_cnt_vct instead of using
arch_get_cnt_pct.
Change-Id: Ic3cf52a2ca3b0a2f83b926df26cecf479080320c
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable support for esoc interface layer with external
soc components on the msm debug and perf defconfigs.
Change-Id: I33a4b1f8cdda9a287e6715b23da8b3876abc2ab0
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable triggering wdog on kernel panic and enable panic
on data corruption.
Change-Id: I4798ff27ef470225607fdccc15e8fa3a6ebdb1eb
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Disable SPI on msmcortex debug and perf configs
since it fails to compile.
Change-Id: Ia9e4077428a0760f1428b81597503e92402bad2a
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
As per ARM the prefetch for store (prfm pstl1strm) in the arch_spin_trylock
routine can lead to some false positives, decreasing the lock performance.
On the Cortex-A57 / Cortex-A53, if the memory type is Shareable, then any
linefill started by a PST (prefetch for store)/PLDW instruction also causes
the data to be invalidated in other cores, so that the line is ready for
writing. This will also clear the exclusive marker associated with that
cache line (clearing the exclusive monitors).
So, in the scenario where we could have multiple cores trying to acquire
exclusive access to a cacheline, the removal of prefetch would help with
potentially increasing the chances of one of the cores making progress.
Example:
struct {
spinlock_t lock;
atomic_t count;
} x;
We have 2 cores trying to run the below code
spin_lock(&x.lock);
atomic_inc(&x.count);
spin_unlock(&x.lock);
lock and count are part of a struct so they fall into the same cacheline.
The lock function uses the trylock mechanism as part of debug spinlock.
1. Core1 has acquired the spinlock and is performing the ldxr, add, strx
loop in atomic_inc.
2. Core2 are trying to acquire the spinlock.
Core1 | Core2
ldxr | |
| | prfm pstl1strm
add | |
| | ldaxr
stxr (fails) | |
| |
Now, the prfm always clears the exclusive marker for the core1 ldxr,
so the stxr always fails. This prevents core1 from making progress and
releasing the spinlock that core2 is waiting for.
This could potentially go on forever and we end up breaking this pattern
if the timing changes or if an interrupt triggers.
This could happen with more cores trying to acquire the spinlock, cause
more prefetches and make the problem worse.
By removing the prfm, we allow the stxr @core1 to suceed and atomic_inc
completes, allowing core1 to unlock the spinlock and let core2 proceed.
Change-Id: I742ab9b6d98aded628e4dcf4a6ec68b8e2a4ec3e
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[abhimany: resolve minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Currently dump_stack is printed once a spin_bug is detected for rwlock.
So provide an options to trigger a panic or watchdog bite for debugging
rwlock magic corruptions and lockups.
Change-Id: I20807e8eceb8b81635e58701d1f9f9bd36ab5877
[abhimany: replace msm with qcom]
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Currently we cause a BUG_ON once a spin_bug is detected, but
that causes a whole lot of processing and the other CPUs would
have proceeded to perform other actions and the state of the system
is moved by the time we can analyze it.
Provide an option to trigger a watchdog bite instead so that we
can get the traces as close to the issue as possible.
Change-Id: Ic8d692ebd02c6940a3b4e5798463744db20b0026
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Once a spinlock lockup is detected on a CPU, we invoke a Kernel Panic.
During the panic handling, we might see more instances of spinlock
lockup from other CPUs. This causes the dmesg to be cluttered and makes
it cumbersome to detect what exactly happened.
Call spin_bug instead of calling spin_dump directly.
Change-Id: I57857a991345a8dac3cd952463d05129145867a8
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Data corruptions in the kernel often end up in system crashes that
are easier to debug closer to the time of detection. Specifically,
if we do not panic immediately after lock or list corruptions have been
detected, the problem context is lost in the ensuing system mayhem.
Add support for allowing system crash immediately after such corruptions
are detected. The CONFIG option controls the enabling/disabling of the
feature.
Change-Id: I9b2eb62da506a13007acff63e85e9515145909ff
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[abhimany: minor merge conflict resolution]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable the error detection and correction driver for
L1/L2 caches on the ARM Cortex-A cpu clusters.
Change-Id: I8dc9e3719ae9868aaee51ef2186e513a3da1a4f7
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Snapshot cortex-a arm cpu edac driver from msm-3.18@
0922caf50f22e751a05e6d613bb1d0c1dc940d7d
("Merge "usb: dwc3-msm: Fix incorrect roles with
multiple instances")
Also fix up ESR macro usage to follow upstream norms.
Change-Id: Ic5498a1ebc9c9d402baf4b839ed8f427e9510083
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
EDAC provides a mechanism to poll for errors using a callback function
and uses a delayed timer to schedule it. Provide an option to create
a deferrable timer if the error checking is not worth waking up
the cpu from idle.
Change-Id: Ia25216323eabf7fa4b894897c950414006921f3f
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add an EDAC device flag and associated sysfs entries to
allow an EDAC driver to be configured to panic the kernel
if a correctable error is detected. Though correctable
errors (by definition) have no adverse system effects,
a panic may still be useful, since a correctable error may
be indicative of a marginal system state.
Change-Id: I98921469254aa7b999979c1c7d9186286f982a0c
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Add a macro containing the MIDR Primary Part Number value
needed to identify ARM Cortex A72 processors.
Change-Id: I6a0d04930070523c3dba83f3d7869ba75288b531
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
[abhimany: resolve minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Move SCSR register offsets and bit positions specific to SPSS from
driver to device tree entry.
CRs-Fixed: 972423
Change-Id: I9712cc550b858af54c90ae92c8636e1d37b3f993
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
Read back value of QDSP6SS_MEM_PWR_CTL after writing, to comply with
reset sequence specification.
Change-Id: Ib803656355c4d498c83fe5cd017823afc5db2c60
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Update the reset sequence to read and override acc register based on msm
specific value provided in device tree.
Change-Id: I8ed290f5ab5e48e94ef5c8c91fd1d8f8414e86f7
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
This patch adds the code to handle watchdog, err_ready and other
interrupts from secure processor subsystem to the PIL driver.
CRs-Fixed: 972423
Change-Id: I65455229ee14bd4da357358ac3977f2137f3c07e
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
One possible cause of a system error exception is an ECC
error in the CPU's caches. Call the ARM64 EDAC error
handler from the system error exception handler to print
EDAC error syndrome information to the kernel log.
Change-Id: If8757eda0c7fc82b0fccee573cf09627a752fdf3
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[satyap: replace ESR_EL1_* with ESR_ELx_* to align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
LPM modes can fail if there is a pending IPI interrupt at GIC CPU
interface. On some usecases frequent failure of LPM modes can
cause power and performance degradation. Hence, prevent cluster
low power modes when there is a pending IPI on cluster CPUs.
Change-Id: Id8a0ac24e4867ef824e0a6f11d989f1e1a2b0e93
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Update the regulator API used in PCIe endpoint driver for 4.4
kernel upgrade.
Change-Id: Iacca851bfbd7f5a5544b97ac82630d9a2dc5ebfc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support of PCIe Endpoint (EP) mode for mdmcalifornium.
Change-Id: I55c85813e674810d865b444b7e19ce4157cea479
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update check for valid MSI enable and setting using
MSI_ENABLE bit instead of address and data. Host can
set address and data to 0 therefore check if MSI_ENABLE
is set.
Change-Id: I686c3ed155b8c5c843d12a49218f4720655dcc18
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Update the configuration of PCIe PHY based on the version of PHY.
Change-Id: I1faf65c2cc1215cd6ad679d0c4558a17f43db3fc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support to trigger link training based on PCIe PHY version.
Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the phy reset clock for PCIe endpoint mode and add the support
of this optional clock.
Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777
Signed-off-by: Yan He <yanhe@codeaurora.org>
PCIe device ID can't be got from register when the power of the
core is off. Thus, use the saved device ID so that we can turn on
link in the debugfs testing.
Change-Id: I28ec17b4fdf84b130cd32267d097b1c0d7c32aed
Signed-off-by: Yan He <yanhe@codeaurora.org>
Fix the bug of the power status of PCIe core and update the power
status as soon as power is turned on.
Change-Id: Ib5b550c78a630d36049296daf1291065a1a44cd5
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.
Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update the lpeak values of PCIe LDOs based on the updated HW
requirement.
Change-Id: I2f8b63edf3f8571ea960abdebde982324f7f6d74
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update some read-only PCIe registers with non-arbitrary values
which are required by PCIe compliance testing.
Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4
Signed-off-by: Yan He <yanhe@codeaurora.org>
The logging macro has multiple outputs. If we increase the counter
as a parameter to the logging macro, the counter will be increased
for multiple times. The change here fixes this bug.
Change-Id: I321e281b506e35770e222def86f5b04ae0bfdce2
Signed-off-by: Yan He <yanhe@codeaurora.org>
Correct the PME configuration for PCIe endpoint to support D0, D3
hot and D3 cold.
Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e
Signed-off-by: Yan He <yanhe@codeaurora.org>
PCIe client may need to wake up the host when PCIe link is still
on. Add the support to assert wake to host side when PCIe is in
D3hot.
Change-Id: I15ffd5f03183054c7ef5d143757b923f32de0adc
Signed-off-by: Yan He <yanhe@codeaurora.org>
The MSM PCIe endpoint driver enables the PCIe core in endpoint mode
and handles the control signaling with PCIe root complex on host
side.
Change-Id: Ifc2735e061820762c6040eda44089a2dc26fc065
Signed-off-by: Yan He <yanhe@codeaurora.org>
The interrupt controller uses level handler for all its interrupt.
The hardware irq controller confirms to the fasteoi handler type in
that it rearms itself when acknowledged. There is no need to
additionally mask the interrupt while being handled.
Use fasteoi handler type for pmic interrupts. Since fasteoi needs
an irq_eoi callback, use the same function used for irq_ack.
Change-Id: I9a941d8b56ad5698da38e16b2afcf87ef920ebfd
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current driver ensures that no read/write transaction is in progress
while it makes changes to the interrupt regions. This is not necessary
because read/writes over spmi and arbiter interrupt control are
independent operations.
Change-Id: Id6a93eed0aabe55a4b655a2050c31b48327dffe4
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The interrupt controller code in the arbiter disables
the peripheral accumulated interrupt (ACC) bit when none of the
interrupts in the peripheral is enabled.
This is not required since the controller disables the interrupt
at the pmic.
So leave the ACC bit enabled while masking an interrupt. Also
ensure that the ACC bit is enabled while unmasking an interrupt.
There is no issues with enabling ACC bit if it were already enabled.
Change-Id: Idbea562157e65a4dfe0c51b7a25eed5ce000068d
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The random pool relies on devices and other items in the system
to add entropy to the pool. Most of these devices may not be
added until later in the bootup process. This leaves a large
period of time where the random pool may not actually give
random numbers. Add a weak function for devices to override
with their own function to setup the random pool.
Change-Id: I0de63420b11f1dd363ccd0ef6ac0fa4a617a1152
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
As compat_hwcap_str[] doesn't end with 'NULL', c_show()
tries to read the next element even after the end of the
array. So add 'NULL' at the end of compat_hwcap_str[].
Below is the KASan report for referencing.
BUG: KASan: out of bounds access in c_show+0x110/0x248 at addr ffffffc0011f6370
Read of size 8 by task pool-1-thread-1/10526
page:ffffffbac14b39c0 count:1 mapcount:0 mapping: (null) index:0x0
flags: 0x400(reserved)
page dumped because: kasan: bad access detected
Address belongs to variable compat_hwcap_str+0xb0/0xe0
CPU: 0 PID: 10526 Comm: pool-1-thread-1 Tainted: G B W 3.18.18-ga7b28e9-11552-ge4a827f #1
Hardware name: Qualcomm Technologies, Inc. MSM 8996 v2 + PMI8994 MTP (DT)
Call trace:
[<ffffffc000089ec4>] dump_backtrace+0x0/0x1c4
[<ffffffc00008a098>] show_stack+0x10/0x1c
[<ffffffc0011a7c58>] dump_stack+0x74/0xc8
[<ffffffc00020e94c>] kasan_report_error+0x2b0/0x408
[<ffffffc00020eb80>] kasan_report+0x34/0x40
[<ffffffc00020db14>] __asan_load8+0x84/0x90
[<ffffffc000088ae8>] c_show+0x10c/0x248
[<ffffffc000245bb8>] traverse+0x1a8/0x320
[<ffffffc000245dc8>] seq_lseek+0x98/0x148
[<ffffffc00028f4e0>] proc_reg_llseek+0xa0/0xd8
[<ffffffc000217d1c>] vfs_llseek+0x5c/0x70
[<ffffffc000218b0c>] SyS_lseek+0x48/0x80
[<ffffffc000218b50>] compat_SyS_lseek+0xc/0x18
Memory state around the buggy address:
ffffffc0011f6200: 00 00 fa fa fa fa fa fa 00 03 fa fa fa fa fa fa
ffffffc0011f6280: 04 fa fa fa fa fa fa fa 00 00 00 00 00 00 00 00
>ffffffc0011f6300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa fa
^
ffffffc0011f6380: fa fa fa fa 00 00 00 00 00 00 fa fa fa fa fa fa
ffffffc0011f6400: 02 fa fa fa fa fa fa fa 00 00 00 02 fa fa fa fa
Change-Id: I5e2098f9a7a676c47a01baf10de3ac1c86265e69
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
[satyap: trivial merge conflict resolution and move changes
in arch/arm64/kernel from setup.c to cpuinfo.c to
align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Sync the ARM64 edac header to the version found in msm-3.10
as of commit 142c36711024877a2ec1eb13dbbca38503b26ee3 ("edac:
cortex_arm64_edac: Use dbe irq only") to bring in external
EDAC API definitions that were missed during the msm-3.18
upgrade.
Change-Id: If2dc53858d7a30086a95ea5047bd6b18e44f7e09
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Commit ebc4e05c338bde49382c7c46ce6b8a371713862e ("arm64: show
present cpu instead of online cpu in /proc/cpuinfo") did not
have its conflicts against msm-3.18 properly resolved.
Change-Id: I1f4eb1d8a20b2bc142a7f0b8890d383a9552557c
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[satyap: trivial merge conflict resolution and move changes
in arch/arm64/kernel from setup.c to cpuinfo.c to
align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
