When the downstream DP device is physically disconnected, ensure
that all pending events are removed and the event thread is parked.
Reset all the software state so that subsequent connection events
are handled correctly.
CRs-Fixed: 2034023
Change-Id: Ie94b1da903b8e78509220e373bec4ff54026885c
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Current implementation assumes that the first extension
block of the EDID data always has the CEA extension tag.
This is incorrect and can lead to incorrect parsing of
resolution data. Fix this by removing the hardcoding of
the extension tag for the first extension block.
CRs-Fixed: 2027108
Change-Id: I5ef4cdb186591e291b2217db7ccec6f942d79ca4
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Trigger the reading of DPCD if there was a change in the AUX
configuration caused by a failure while reading the EDID.
This is required to ensure the integrity and validity
of the sink capabilities read that will subsequently be used
to establish the mainlink.
CRs-Fixed: 2006096
Change-Id: If3a51b5efd9124fd20dc9860e5f2cdb4e466a2c6
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Ignore the PHY AUX stop error if we receive this error
during an AUX transaction. We can safely ignore this
error and proceed to read the buffered data from the
hardware since this error happens after the data has
been received by the AUX controller hardware.
CRs-Fixed: 2006096
Change-Id: Idb3f0e59b572be565e7572db500699471665f287
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Ensure that all previous interrupt status are cleared before
triggering a new aux transaction, and do not set the
NO_SEND_STOP request bit for read transactions to align with
the hardware programming recommendations.
CRs-Fixed: 2006096
Change-Id: Icc17ac7b09d70ab5b330189be38fa32e3bff850e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Each block of EDID data is usually 128 bytes long. Reading
each block in a single burst can sometimes result in incorrect
or corrupted data returned from the sink. Add support to read
EDID in shorter burst sizes and set the default burst size
to 16 bytes.
CRs-Fixed: 2006096
Change-Id: I681f2d2eb01de11eadc1857dd5089cbe35befad2
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the EDID read sequence to first write the offset to
request the appropriate EDID block prior to reading the EDID
block data. In addition, write the correct segment address
when reading more than two extension blocks.
CRs-Fixed: 2006096
Change-Id: Ic4b2bd4d4cf9da5e247c5735b4e768b9e2b87b27
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Retry AUX read/write transactions that have failed either due
to the AUX controller hardware indicating an error via the ISR,
or due to a software based timeout while waiting for transaction
completion. The transaction retry strategy is as follows: first
repeat the transaction using the same PHY AUX settings, and then
retry the transaction using updated PHY AUX settings if repeating
the transaction has failed.
CRs-Fixed: 2006096
Change-Id: Id9c3c7ae1ab320540545b9c178d947a3cd023079
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Make the parsing of the AUX controller configurations more
extensible by adding support for multiple settings per configuration,
as well as the parsing of the register offsets. This enables the
extension to support different targets, and combinations of AUX
controller settings depending on the use case.
CRs-Fixed: 2006096
Change-Id: I4e6b623a4d9fafcfcc89477dfa57880eb798c350
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Increase the AUX controller hardware timeout limits to the
maximum value supported. This increases the AUX controller
hardware's robustness in handling transactions in the face
of differing timing from one DisplayPort sink to another.
CRs-Fixed: 2006096
Change-Id: Ia0da13720526a96f3a88a849043a3ffbb1185cf7
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add interrupt handling for PHY AUX errors that might
happen during AUX communication. Read the interrupt
status and clear it before initiating the next AUX
transaction. This will help identify any issues that
result in AUX transaction failures.
CRs-Fixed: 2006096
Change-Id: I0733bfb163c8c3c108002fbe4309e36dc105ccb8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
A branch device usually notifies a change in downstream connections
using the HPD IRQ pulse. Handle this by checking for a change in
downstream sink count and appropriately handling EDID reads. It is
also possible that the branch device may not have any local EDID.
In such cases, when the downstream sink count is zero, do not read
EDID.
CRs-Fixed: 1112711
Change-Id: I230560c995d7c3b395e37aef5483e5468e1d1dec
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Implement a failsafe mechanism that will prevent the DisplayPort
driver from entering an irrecoverable state in the face of
delayed power off/on events from the display framework. For example,
the driver must indefinitely postpone the handling of other events
from the sink until the power off event is complete, ensuring that
there is no interleaving of events that could lead to a bad state,
or un-clocked register access.
CRs-Fixed: 2006096
Change-Id: I1bfa887ba5ee94cbf44c87aa0d60766cafc854b4
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
EDID utility always lists the default resolution as part of the list
of available modes. If the client does not specify a default resolution
it can result in incorrect behavior. Ensure that the Display Port
driver always initialized with a default resolution.
CRs-Fixed: 2030915
Change-Id: Ib6c75d655e6fcbd5c792ca1aa9da6b08ba2f416e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Skip the transfer unit setup and the routine to wait for the
video ready interrupt as link training tests do not require
video frames to be sent.
CRs-Fixed: 2006096
Change-Id: Ibf9cda18f8740890f384b1d99f8d00b4692ab74d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.
Change-Id: I6df35bbe18b0c42b43f38b9dd85c3502b2038928
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
When the supply to PLL digital domain is turned off,
it can result in certain PLL registers to get corrupted.
Make sure to re-program the PLL registers to the
power-on-reset value before starting to program the PLL again
to ensure that it locks reliably.
Change-Id: I63cac884cf11eae60b187f83654f5922a3342d66
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
During clock gating (ufshcd_gate_work()), we first put the link hibern8 by
calling ufshcd_uic_hibern8_enter() and if ufshcd_uic_hibern8_enter()
returns success (0) then we gate all the clocks.
Now let’s zoom in to what ufshcd_uic_hibern8_enter() does internally:
It calls __ufshcd_uic_hibern8_enter() which on detecting the LINERESET,
initiates the full recovery and puts the link back to highest HS gear and
returns success (0) to ufshcd_uic_hibern8_enter() which is the issue as
link is still in active state due to recovery!
Now ufshcd_uic_hibern8_enter() returns success to ufshcd_gate_work() and
hence it goes ahead with gating the UFS clock while link is still in active
state hence I believe controller would raise UIC error interrupts. But when
we service the interrupt, clocks might have already been disabled!
This change fixes for this by returning failure from
__ufshcd_uic_hibern8_enter() if recovery succeeds as link is still not in
hibern8, upon receiving the error ufshcd_hibern8_enter() would initiate
retry to put the link state back into hibern8.
Change-Id: Ib550fb791fa4c582b8f2d317a7f5f7594acb0872
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add support to handle system error and shutdown notification
from MHI host.
CRs-Fixed: 2022936
Change-Id: Id36097dffd7571490d7d53d2e496bfe024702a42
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Two notify requests are being queued for one available modem
response. So for the first GET_ENCAPSULATED_RESPONSE we provide
the host with the available response. Now for the next
GET_ENCAPSULATED_COMMAND we notify the host that the response is
available even before the modem is ready with a response because
of the extra notify request queued on the interrupt endpoint.
This causes a STALL for the next GET_ENCAPSULATED_RESPONSE request.
This is caused because we are queueing a notify request from the
completion handler of the interrupt endpoint request when the
response queue is not empty.
Fix this by queuing a notify request when a new response is
available only after the current resposne is send to the Host.
Change-Id: If84bc315f2be910503328cc6b0e21be342c6eb37
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Add support to handle system error and shutdown
notifications from mhi host.
CRs-Fixed: 1097560
Change-Id: Ied6c907586aa4dc2ed3b1a7c19305877144b3b21
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Driver register doesn't have to be synchronous with probe call
back. Keep the driver registered till unregister gets called and
never reset ops during probe failure.
CRs-fixed: 2029329
Change-Id: I61331c7f33b29b0bc4833a8e4c52ee94f17660e7
Signed-off-by: Anurag Chouhan <achouhan@codeaurora.org>
Soundwire control data is NULL if there is no soundwire slave
device enumerated.
Add null check to avoid panic.
Change-Id: Ief60d69c36c2a9831825f38da2c9a3f6dd5f13dc
CRs-Fixed: 2020293
Signed-off-by: Meng Wang <mwang@codeaurora.org>
