Add support to update the HDMI AVI infoframe to use
BT2020 encoding during HDR video playback.
This is required as per the spec to ensure that the
AVI infoframe correctly indicates the content being
shown.
Also make sure to change and restore the YCC
quantization bits in case of override.
Change-Id: Iadacc2fac6252b5f5cbfcc39a122118f738d3113
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
The CSC matrix used in the CDM block should be
updated to BT2020 format from the default value
during HDR video playback.
Add support in the SDE driver to enable switching
CSC matrix of CDM block to BT2020 during start of
HDR playback and restore it at the stop of the
playback to the default CSC.
Change-Id: Ic589380188ddef8ada2c8bbc0ca945bb1f319c85
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Currently only BT601 CSC matrix is available for use
in the SDE driver.
Add BT709, BT2020 CSC matrix definitions to SDE driver.
These shall be used during different use-cases such as
HDR video playback by switching the CSC matrix based on the
use-case.
Change-Id: I70a543193d08217cbdb6c4af739b3777dde4a25d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
CDM block is always using a limited quantization range
matrix.
This can be overridden to use a full range matrix if
the sink supports override capability or the mode is a
non-CEA mode.
Adjust the matrix selection logic to accommodate these
conditions.
Change-Id: I708412a923fb0d47e798f35ebe14b4c2f1a72fc9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Since 'timestamp' is of unsigned int type, for larger timestamp
the format specifier %d can show negative values. Fix this by
using %u format specifier for timestamp.
Change-Id: I621dfd4843099cb27436006500fe3342d1d5ddf4
Signed-off-by: Abhilash Kumar <krabhi@codeaurora.org>
Provide support to enable/disable sw jeita using a power supply
property.
Change-Id: Id1c2a4bcd8caece5ed7591dc5ab5bf3ac2207cba
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Disable sending dummy BDF(board data file). Enforce to use real BDF
by default.
Change-Id: Ib0cf267af8ddea8a702f8ac6774063466094f52e
CRs-fixed: 2059087
Signed-off-by: Yue Ma <yuem@codeaurora.org>
On each sg of secure CMA buffer to set/clear page private bit,
we should use the sg_page(sg) rather than sg_page(sgt->sgl).
Change-Id: I05300d9d3a0931d2a0c113f945b45136e0dea01e
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Core IPA driver passes wrong end-point index to HAL
when generating aggregation force close parameters
values. Fixed the call to pass the correct index.
CRs-Fixed: 2082839
Change-Id: Icc0fd2ce8a23bf0e3334f54b27b850ebf92b58a1
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
After finishing initialization during PCIe probe, there is no need to
keep PCIe link up. Hence suspend PCIe link and power off device after
PCIe probe for QCA6290 chipset.
Change-Id: I1b07d7c9ef4c3a15ba1eb409a4c64f905e83dae4
Signed-off-by: Yue Ma <yuem@codeaurora.org>
The vibrator HAL expects vibration to be disabled when the 'enable'
time specified is 0. Fix this.
CRs-Fixed: 2083994
Change-Id: I12843233da5429ed2fd53f33617952b1dd0ddcd5
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Currently, when scrambler is disabled the TMDS clock ratio bit
is left untouched. Ideally the sink should reset this bit during
hot plug OR no-signal cases. However, the HDMI spec requires this
bit to be explicitly reset by the source.
Add support to reset this bit during scrambler disable.
Change-Id: I092f6cae84653940e2bdb9100df5e384084cf938
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
As per SMC Calling Convention, X4/W4, X5/W5 & X6/W6 registers
return state is unpredictable. But, inline assembly in scm
driver did not correctly specify output markers, which is
causing compiler to move instructions around when clang is
used to compile, which inturn causing deadlock and boot issue
during firmware loading. Add X4/W4, X5/W5 & X6/W6 registers
to output operand list to fix the deadlock during firmware
loading.
Change-Id: I1e4d51a58cd34c31fc63bcd21a20bfd15498bdc3
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
PD down notifications reaches APPS only after WLAN HW is
reset. Because of this, there is a small window of time
in which APPS may try to access WLAN HW Copy Engine
registers and get into exception. To avoid this, FW has
implemented 2 stage reset sequence in which first HW is
halted rather than reset and then when FW PD is started
again, reset sequence is executed. Because of the 2
stage reset sequence, WLAN shutdown call back also needs
to be delayed as there may be some buffers submitted to
hardware and if they are freed then again HW exception
may be seen. Delay the shutdown call back till FW ready
happens at this time HW should be reset and clean state.
CRs-fixed: 2056443
Change-Id: Ie587f98d574f7c0a49a8480449fed44c1f4ab816
Signed-off-by: Anurag Chouhan <achouhan@codeaurora.org>
