Move SCSR register offsets and bit positions specific to SPSS from
driver to device tree entry.
CRs-Fixed: 972423
Change-Id: I9712cc550b858af54c90ae92c8636e1d37b3f993
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
Read back value of QDSP6SS_MEM_PWR_CTL after writing, to comply with
reset sequence specification.
Change-Id: Ib803656355c4d498c83fe5cd017823afc5db2c60
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Update the reset sequence to read and override acc register based on msm
specific value provided in device tree.
Change-Id: I8ed290f5ab5e48e94ef5c8c91fd1d8f8414e86f7
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
This patch adds the code to handle watchdog, err_ready and other
interrupts from secure processor subsystem to the PIL driver.
CRs-Fixed: 972423
Change-Id: I65455229ee14bd4da357358ac3977f2137f3c07e
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
One possible cause of a system error exception is an ECC
error in the CPU's caches. Call the ARM64 EDAC error
handler from the system error exception handler to print
EDAC error syndrome information to the kernel log.
Change-Id: If8757eda0c7fc82b0fccee573cf09627a752fdf3
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[satyap: replace ESR_EL1_* with ESR_ELx_* to align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
LPM modes can fail if there is a pending IPI interrupt at GIC CPU
interface. On some usecases frequent failure of LPM modes can
cause power and performance degradation. Hence, prevent cluster
low power modes when there is a pending IPI on cluster CPUs.
Change-Id: Id8a0ac24e4867ef824e0a6f11d989f1e1a2b0e93
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Update the regulator API used in PCIe endpoint driver for 4.4
kernel upgrade.
Change-Id: Iacca851bfbd7f5a5544b97ac82630d9a2dc5ebfc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support of PCIe Endpoint (EP) mode for mdmcalifornium.
Change-Id: I55c85813e674810d865b444b7e19ce4157cea479
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update check for valid MSI enable and setting using
MSI_ENABLE bit instead of address and data. Host can
set address and data to 0 therefore check if MSI_ENABLE
is set.
Change-Id: I686c3ed155b8c5c843d12a49218f4720655dcc18
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Update the configuration of PCIe PHY based on the version of PHY.
Change-Id: I1faf65c2cc1215cd6ad679d0c4558a17f43db3fc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support to trigger link training based on PCIe PHY version.
Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the phy reset clock for PCIe endpoint mode and add the support
of this optional clock.
Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777
Signed-off-by: Yan He <yanhe@codeaurora.org>
PCIe device ID can't be got from register when the power of the
core is off. Thus, use the saved device ID so that we can turn on
link in the debugfs testing.
Change-Id: I28ec17b4fdf84b130cd32267d097b1c0d7c32aed
Signed-off-by: Yan He <yanhe@codeaurora.org>
Fix the bug of the power status of PCIe core and update the power
status as soon as power is turned on.
Change-Id: Ib5b550c78a630d36049296daf1291065a1a44cd5
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.
Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update the lpeak values of PCIe LDOs based on the updated HW
requirement.
Change-Id: I2f8b63edf3f8571ea960abdebde982324f7f6d74
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update some read-only PCIe registers with non-arbitrary values
which are required by PCIe compliance testing.
Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4
Signed-off-by: Yan He <yanhe@codeaurora.org>
The logging macro has multiple outputs. If we increase the counter
as a parameter to the logging macro, the counter will be increased
for multiple times. The change here fixes this bug.
Change-Id: I321e281b506e35770e222def86f5b04ae0bfdce2
Signed-off-by: Yan He <yanhe@codeaurora.org>
Correct the PME configuration for PCIe endpoint to support D0, D3
hot and D3 cold.
Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e
Signed-off-by: Yan He <yanhe@codeaurora.org>
PCIe client may need to wake up the host when PCIe link is still
on. Add the support to assert wake to host side when PCIe is in
D3hot.
Change-Id: I15ffd5f03183054c7ef5d143757b923f32de0adc
Signed-off-by: Yan He <yanhe@codeaurora.org>
The MSM PCIe endpoint driver enables the PCIe core in endpoint mode
and handles the control signaling with PCIe root complex on host
side.
Change-Id: Ifc2735e061820762c6040eda44089a2dc26fc065
Signed-off-by: Yan He <yanhe@codeaurora.org>
The interrupt controller uses level handler for all its interrupt.
The hardware irq controller confirms to the fasteoi handler type in
that it rearms itself when acknowledged. There is no need to
additionally mask the interrupt while being handled.
Use fasteoi handler type for pmic interrupts. Since fasteoi needs
an irq_eoi callback, use the same function used for irq_ack.
Change-Id: I9a941d8b56ad5698da38e16b2afcf87ef920ebfd
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current driver ensures that no read/write transaction is in progress
while it makes changes to the interrupt regions. This is not necessary
because read/writes over spmi and arbiter interrupt control are
independent operations.
Change-Id: Id6a93eed0aabe55a4b655a2050c31b48327dffe4
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The interrupt controller code in the arbiter disables
the peripheral accumulated interrupt (ACC) bit when none of the
interrupts in the peripheral is enabled.
This is not required since the controller disables the interrupt
at the pmic.
So leave the ACC bit enabled while masking an interrupt. Also
ensure that the ACC bit is enabled while unmasking an interrupt.
There is no issues with enabling ACC bit if it were already enabled.
Change-Id: Idbea562157e65a4dfe0c51b7a25eed5ce000068d
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The random pool relies on devices and other items in the system
to add entropy to the pool. Most of these devices may not be
added until later in the bootup process. This leaves a large
period of time where the random pool may not actually give
random numbers. Add a weak function for devices to override
with their own function to setup the random pool.
Change-Id: I0de63420b11f1dd363ccd0ef6ac0fa4a617a1152
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
As compat_hwcap_str[] doesn't end with 'NULL', c_show()
tries to read the next element even after the end of the
array. So add 'NULL' at the end of compat_hwcap_str[].
Below is the KASan report for referencing.
BUG: KASan: out of bounds access in c_show+0x110/0x248 at addr ffffffc0011f6370
Read of size 8 by task pool-1-thread-1/10526
page:ffffffbac14b39c0 count:1 mapcount:0 mapping: (null) index:0x0
flags: 0x400(reserved)
page dumped because: kasan: bad access detected
Address belongs to variable compat_hwcap_str+0xb0/0xe0
CPU: 0 PID: 10526 Comm: pool-1-thread-1 Tainted: G B W 3.18.18-ga7b28e9-11552-ge4a827f #1
Hardware name: Qualcomm Technologies, Inc. MSM 8996 v2 + PMI8994 MTP (DT)
Call trace:
[<ffffffc000089ec4>] dump_backtrace+0x0/0x1c4
[<ffffffc00008a098>] show_stack+0x10/0x1c
[<ffffffc0011a7c58>] dump_stack+0x74/0xc8
[<ffffffc00020e94c>] kasan_report_error+0x2b0/0x408
[<ffffffc00020eb80>] kasan_report+0x34/0x40
[<ffffffc00020db14>] __asan_load8+0x84/0x90
[<ffffffc000088ae8>] c_show+0x10c/0x248
[<ffffffc000245bb8>] traverse+0x1a8/0x320
[<ffffffc000245dc8>] seq_lseek+0x98/0x148
[<ffffffc00028f4e0>] proc_reg_llseek+0xa0/0xd8
[<ffffffc000217d1c>] vfs_llseek+0x5c/0x70
[<ffffffc000218b0c>] SyS_lseek+0x48/0x80
[<ffffffc000218b50>] compat_SyS_lseek+0xc/0x18
Memory state around the buggy address:
ffffffc0011f6200: 00 00 fa fa fa fa fa fa 00 03 fa fa fa fa fa fa
ffffffc0011f6280: 04 fa fa fa fa fa fa fa 00 00 00 00 00 00 00 00
>ffffffc0011f6300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa fa
^
ffffffc0011f6380: fa fa fa fa 00 00 00 00 00 00 fa fa fa fa fa fa
ffffffc0011f6400: 02 fa fa fa fa fa fa fa 00 00 00 02 fa fa fa fa
Change-Id: I5e2098f9a7a676c47a01baf10de3ac1c86265e69
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
[satyap: trivial merge conflict resolution and move changes
in arch/arm64/kernel from setup.c to cpuinfo.c to
align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Sync the ARM64 edac header to the version found in msm-3.10
as of commit 142c36711024877a2ec1eb13dbbca38503b26ee3 ("edac:
cortex_arm64_edac: Use dbe irq only") to bring in external
EDAC API definitions that were missed during the msm-3.18
upgrade.
Change-Id: If2dc53858d7a30086a95ea5047bd6b18e44f7e09
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Commit ebc4e05c338bde49382c7c46ce6b8a371713862e ("arm64: show
present cpu instead of online cpu in /proc/cpuinfo") did not
have its conflicts against msm-3.18 properly resolved.
Change-Id: I1f4eb1d8a20b2bc142a7f0b8890d383a9552557c
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[satyap: trivial merge conflict resolution and move changes
in arch/arm64/kernel from setup.c to cpuinfo.c to
align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Moving towards device tree and arm single binary refering to
machine descriptor name for hardware id information under
/proc/cpuinfo is not suitable for certain soc vendors. Add a
hook for soc vendors to supply a per-soc hardware read method.
Change-Id: Ifcccdffa3c0e1e8b5f96837eb1c023e468d4c287
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[satyap: trivial merge conflict resolution and move changes
in arch/arm64/kernel from setup.c to cpuinfo.c to
align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
The existing timeout values for the various GPMU interactions seems
to have been a tad optimistic for all conditions. Increase them to
cover measured worse case scenarios.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Make several changes to build the GPU driver for 4.4:
- Rename CONFIG_MSM to CONFIG_QCOM where applicable
- Add msm_kgsl.h to the Kbuild exports
- Remove linux/coresight_of.h (as it has been merged into
coresight.h) and remove the .owner member of the
coresight_desc struct.
- Use the new location for the sync.h file (in staging)
- Remove an unused sync function
- Move oneshot_sync.h inside of #ifdef wrappers
Signed-off-by: Jordan Crouse <jcrouse@codeauorora.org>
Snapshot of the Qualcomm GPU devfreq governors and support
as of msm-3.18 commit e70ad0cd5efd
("Promotion of kernel.lnx.3.18-151201.").
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Level based governors may need to perform this lookup to
interpret the current frequency of the device.
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: Vladimir Razgulin <vrazguli@codeaurora.org>
Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit
commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201.").
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The file that defines of_get_coresight_platform_data() is indeed
dependent on CONFIG_OF but the entire coresight directory depends
on CONFIG_CORESIGHT so both need to be enabled to make the symbol
resolve.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add support for filesystem passthrough read/write of files
when enabled in userspace through the option FUSE_PASSTHROUGH.
There are many FUSE based filesystems that perform checks or
enforce policy or perform some kind of decision making in certain
functions like the "open" call but simply act as a "passthrough"
when performing operations such as read or write.
When FUSE_PASSTHROUGH is enabled all the reads and writes
to the fuse mount point go directly to the passthrough filesystem
i.e a native filesystem that actually hosts the files rather than
through the fuse daemon. All requests that aren't read/write still
go thought the userspace code.
This allows for significantly better performance on read and writes.
The difference in performance between fuse and the native lower
filesystem is negligible.
There is also a significant cpu/power savings that is achieved which
is really important on embedded systems that use fuse for I/O.
Changelog:
v5:
Fix the check when setting the passthrough file
[Found when testing by Mike Shal]
v3 and v4:
Use the fs_stack_depth to prevent further stacking and a minor fix
[Fix suggested by Jann Horn]
v2:
Changed the feature name to passthrough from stacked_io
[Proposed by Linus Torvalds]
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
A new struct element was added during the kernel 4.4 upgrade.
Ensure that it is set during dynamic attach.
Change-Id: I0150aebe4a67728945890be2b547a6cbb9bd5306
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Taken as of kernel version "e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1"
on msm-3.18.
Change-Id: I91bdb35429af8159e58bb6fb9e2e52f16d625c4b
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Add support to read device names from device tree entries.
This allows using same names for CoreSight devices across different
targets.
Change-Id: Ide3da74533051db38e9a6c5904a7cab42b3be6c1
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Use 'enable' instead of 'enable_source' and 'curr_sink' instead of
'enable_sink attributes to align it with MSM implementation.
This change ensures same device node interface for host tools
between MSM and upstream Coresight driver implementation.
Change-Id: I5267d2ad92e76607e0ac1bd0e9ef63c0a89cfe7f
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to configure ETR device in scatter-gather mode.
In scatter-gather mode trace buffer can be configured to use bigger
buffer size without need of bigger contiguous memory.
Change-Id: I3ce654392d2b75d24f7982638e53c2aab27d4a0e
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
