Currently hardware based OTG soft start will fail when enabling OTG with
high capacitance.
Fix this by implementing a software based OTG soft start sequence in
addition to the underlying hardware OTG soft start.
This soft start workaround will begin when an OTG over-current interrupt
is triggered.
Change-Id: I2f3fd5f1bb6e792b2b353eb241d83548e33f563b
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The threshold comparators should be set to "<=". Set them.
Change-Id: I45cf6dd7f165d20e2f2dbc6fce7fd321b4ac145a
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The temperature change IRQ is used to update the parallel power supply
when the temperature of the connector changes. Enable it.
Change-Id: I26582ffc2c98183c75f5c302386416e840bd6ed0
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The connector thermal regulation source must be enabled in order to
receive temperature-change interrupts. Enable it.
Change-Id: I9bb2d3eaf3bba1b1f40bfd724060f2fa437235b5
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add a device tree property qcom,connector-temp-max-mdegc to configure
the connector temperature at which mitigation should start.
This will set the thresholds for when the temperature-change IRQ will
fire.
Change-Id: I47df477b56a6654fbf94b5bb0f7dfdfb80e2f16e
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Use the CONNECTOR_THERM_ZONE property to show the current thermal zone
of the USB connector temperature.
Change-Id: Ia9a85055d68ed08aa9be5b2b66e3e6389ec2e6c3
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The CONNECTOR_THERM_ZONE property shows which thermal zone the
connector temperature is currently in.
Change-Id: I669344feea13f34f98ee808cae5649766543201a
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The temperature change IRQ is used to notify the CTM driver that the
connector temperature has changed. Enable it.
Change-Id: Ibda88fcac6044c0f9a1db96be70b7e7f99e6fb73
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The charger temperature threshold should be configured for thermal
balancing. Add a device tree property to configure the temperature
threshold. A default value will be used in the absence of this property.
Change-Id: I5d64a8012a9c13c578714d91f1e7e4426cef235a
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The hardware conversion triggers are required for thermal regulation.
Enable them.
Change-Id: I4172f7ae8df437ba3a49e6abae587298bc11d78b
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
The TADC hardware supports configuring temperature thresholds. Add
support for configuring these thresholds via the IIO framework.
Change-Id: Ib673965eb9b8265874580c8c26f72c85590151c2
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Update the nt35597 truly panel init sequence to reduce the
high latency issue seen across suspend resume cycles on
SDM660 target.
Change-Id: I0d71cebd5571fac293a8b0f401d882342fbd9106
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Recovery can be initiated any time and can happen during driver
register also. With current implementation, if recovery starts
just before driver register then probe call back will not be
called as FW is not ready yet but probe call back will not be
called even after FW ready indication. Fix this case by calling
probe call back after FW ready if driver is registered but probe
call back is not called during driver register.
CRs-fixed: 2002797
Change-Id: Ia1ea812a1bac3204ad95a62b7c6e55511753f2db
Signed-off-by: Prashanth Bhatta <bhattap@codeaurora.org>
Update truly FHD panel init sequence to fix corruption
issues. Also enable dfps feature for the video mode panel
on SDM660 target with the updated sequence.
Change-Id: Ife010a0fccefad802877fd50f222587be36d24aa
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Display port pixel clock source is required to propagate the set rate to
parent, so update the flags for the same. The lowsvs frequency has got
updated to 154MHz, update the same.
Change-Id: I67a5ff3b5fb18c2ce986c5f431f4e41a78fe13a5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The display port PLL generates only limited set of frequency combinations.
As fractional dividers are not required to be used, update the RCG ops to
take care of the same.
Change-Id: I601273fee044ef128dbc7c2e23bc2d8ce10e31dc
Signed-off-by: Taniya Das <tdas@codeaurora.org>
