When caching the SSPP(source surface post processing) pipes parameters
pipe type should be checked for all PP features. SSPP config
function was checking the pipe type for multiple features which results
in code duplication. This change removes the code duplication by moving
the checks to top of the function.
Change-Id: I5f817ba881ab3763132360a2870830e0c40c887b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Caching parameters passed by driver client for source surface IGC
(inverse gamma correction) shouldn't be tied to a version of IGC
feature. Based on version passed by driver client driver will allocate
the payload and cache the parameters. This change adds support for
caching based on the IGC version.
Change-Id: I0d120716d71ef378a7314d06823621e069f58b71
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
PCC(polynomial color correction) feature is supported in SSPP(source
surface post processing) MDP block of thulium. This change enables the
caching of PCC params passed by driver client and programming the SSPP
pcc hardware block.
Change-Id: I3798becf7ed675c32a90bc7cefa415c055516d72
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Picture Adjustment (PA) global and memory color adjustments are supported
on source side VIG pipes in MDP. Clients of MDP driver can enable the
feature using overlay ioctl interface. This change adds support for
clients of the driver to enable the feature.
Change-Id: If961bb20167a7d08bf77dc4807acb46f38094f63
Signed-off-by: Benet Clark <benetc@codeaurora.org>
The PP features in SSPP, specifically VIG pipe, use config ops
to specify which features to configure. However, these ops are
also used as the dirty flag for writing the registers. Therefore,
if there is an error while caching the parameters, the dirty flags
for all PP pipe features should be removed.
Change-Id: I0ac04308c1644332932e90c3661158348f60eb37
Signed-off-by: Benet Clark <benetc@codeaurora.org>
The PP setup in SSPP VIG pipes is not modular. It currently configures
all the registers and opmode bits in sequential, arbitrary order. This
change moves the VIG opmode config to a separate function from the VIG
pipe setup, for pp_sts based features only. This change also cleans up
the VIG pipe setup in order to make thulium upgrade easier.
Change-Id: I3c6bfc1d8a337c7f1756492a35c401a97e20d810
Signed-off-by: Benet Clark <benetc@codeaurora.org>
In case of CEA extension block is not correct or corrupted, fall
back to block 0 to read the resolutions supported.
Change-Id: I2b63ff1f918b3ece89ab35eb4a64d4ac96aaeabe
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Every time the SMP requirement of a pipe changes, release current
SMP's and re-allocate only as much needed.
Change-Id: I620278a0480c14724965cc2dad0a255177891ac3
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
It's not necessary for SSPP and Layer mixer to support same width.
Add a new property for maximum width supported by SSPP and
use it for validating the pipe configurations. Expose the same property
to the user space client to make the decision on using one or
two pipes for composing a layer.
Change-Id: I8a550c25078036158fcf330eb9083fc50e24c714
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[imaund@codeaurora.org: Resolved context conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Current driver checks if some video interface is connected
in order to apply a fudge factor.
This is expected for real time interfaces, but non real
time interfaces should not account for this extra bandwidth.
This fix adds a check to make sure that for non real time
interfaces the fudge factor does not get applied.
Change-Id: Ib01d12f4e7749f4e083fa09f6392896313978d72
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Currently LAB/IBB is controlled through WLED which
only support LCD type. In order to support Amoled
panel, LAB/IBB need to be controlled independently
from WLED.
Change-Id: I4eca47f60d1333d2a928109c3ae4cbeb454b49dc
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Current idle detection logic starts timer at beginning of the frame, but
if producer (GPU or others) takes some time to release fences we may be
signaling idle timeout before we even posted contents on the screen.
Revisit logic to wait until after fences have been signaled before
signaling idle timeout.
Change-Id: Id5ec0e334212484b257149727af0325b7acc3e86
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
BUG will panic without giving the state of the display hardware at
the point where it happens. Instead use XLOG which will provide more
details about the hardware and can be disabled to allow recovery
sequence to kick in.
Change-Id: Id4602394f1096d5f40321c14c4d5af48675468e8
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
DSi-1 is responsible for triggering both controllers to send
dcs command to both panels at same time when sync-wait-broadcast
enabled. Therefore 2A/2B dcs command need to be sent to panels
through dsi-1 when both roi-merge and sync-wait-broadcast enabled.
CRs-Fixed: 769487
Change-Id: I2ad02e8c63c1f214513583060103901e28b92e61
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Underruns are observed on 8974 with HDMI connected since the
combined BW of primary and HDMI interface exceeds the
threshold BW. Fail the prepare call under such conditions so
that fallback happens.
Change-Id: I1217c862c344871868e1fabbb7ba51f6814c1e04
Signed-off-by: Vineet Bajaj <vbajaj@codeaurora.org>
Rotator destination format can be different depending
in the source format. Previously we were only checking
the destination format for bwc or rot90, but this is
wrong since there are other scenarios like rotator
downscaling, where we need to get the destination
pixel format, otherwise we get some misconfiguration
and corruption is observed. This change makes sure
that always we get the expected destination format
for the rotator.
Change-Id: I9e3e331e011fcf8301183560ac41fd94cae833c5
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Release kick off and unlock ov_lock before waiting for wb
done so that next prepare can start.
Change-Id: If4d53d81a5d77ffc9bcb1e0582f9741b258aedcd
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
If the cont_splash_enabled added with "&&" for backlight update
check then the unset_bl_level will be set 0 in all cases. Fix this
to add "||" as condition check instead of "&&".
Change-Id: I9365bd9b9beaada78b49e9e79046715f05ea5b72
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Previously, gamma correction dirty bit is not properly set for
all the use cases, which is causing the disable ioctl for gamma
correction to fail. This change fixes the issue in disable ioctl.
Change-Id: I4901c05d305577857862f6b5316fa59ececcc842
Signed-off-by: Ping Li <pingli@codeaurora.org>
Initialize maximum number of zorder's programmable by the client
to 4 for msm8992 target.
Change-Id: I090ddf709322c91fd40e9403ad7471d87c5e82af
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Use target specific ping pong buffer register offsets instead
of hard coded ones to program control and config parameters.
Change-Id: Id446452d6ff42e886b8e3232a1143c1b0a742489
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[imaund@codeaurora.org: Resolved context conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
This change adds support to autorefresh the command mode panels
without having to manually issue a kickoff. We need to enable
sys/class/graphics/fb0/msm_cmd_autorefresh_en to configure after
how many idle ticks(read ptr/vsync) should we trigger a frame.
e.g. If we want to send an update at 60fps
we need to echo 1 > sys/class/graphics/fb0/msm_cmd_autorefresh_en
to disable we need to echo 0 >
sys/class/graphics/fb0/msm_cmd_autorefresh_en
Change-Id: Ib0cda1142f8fadfa6cad5e61e0c7fb36fe43aca1
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
[imaund@codeaurora.org: Updated INIT_COMPLETION call to
reinit_completion]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
The new sequence is intended to improve pll locking time. This patch
is part of new sequence for phy ctrl in DSI driver side.
Change-Id: I9c38d98f1e32cfa1e5f4d12156a6fa9cb15e3049
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed msm8994-mdss.dtsi changes from this commit]
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Both in dual dsi and single dsi case, only dsi0's phy regulators
need to be programmed. Reduce the dependency between the two
dsi's for enabling and disabling the dsi0's phy regulators.
Add dsi0's phy regulator base to both dsi's as it can
independently program it, if the panel is boot with dsi1 or dsi0.
Change-Id: I04bfa4025fb5e20e3624577275d01b37a9f723bf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
[imaund@codeaurora.org: Removed changes to files that do not exist
in msm-3.14]
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed apq8084-mdss.dtsi, msm8226-mdss.dtsi, msm8916-mdss.dtsi,
msm8939-mdss.dtsi, msm8992-mdss.dtsi, msm8994-mdss.dtsi
changes from this commit]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Function mdss_mdp_ctl_perf_get_transaction_status tracks mdp
status whether a commit is currently in progress. If it is
then we don't schedule the work queue, otherwise schedule it.
Cases where work queue is not scheduled, waitforpp takes care
of notify frame done. In case of last frame update, work
queue takes care of notify frame done.
Change-Id: I98c9af4ec412f06d48e0ae57e5973bf34be9110d
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Add debugfs nodes to enable and configure fbc
for simulation panels.
Change-Id: Ie469f10ff6285fa4778357505d0b973ba677e38e
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
[cip@codeaurora.org: Use debugfs_create_u32 for u32 variables]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
When there are any issues halting pipes during free, we go into recovery
sequence where pipes that cannot be cleaned up are forcefully staged to
get recovered. After this we need to remove them to complete recovery
sequence, otherwise it will remain active which is not the intention.
Also add check to ensure we catch such cases for all dual mixer cases.
Change-Id: If9fb04130de286eb1bf9a8171461df693dc2493d
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
There is possibility that the time of mdp flush bit set
and the time of dsi flush bit are cross vsync boundary.
Therefore wait4vsync is needed to guarantee both flush
bits are set within same vsync period regardless of mdp
revision.
CRs-Fixed: 766349
Change-Id: I5fd1b7c94f119d8e5f1fdd2ceb5476ed27a730fc
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Add maximum bandwidth per pipe, maximum mdp clock rate
and mdp clock fudge factor to the capabilities exposed
to the display driver user space.
Change-Id: I3266bcaf7df8caa127cbeebc8430e7b3a6e3ecf7
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Horizontal scalar support on VIG pipe was only intended for 8092. Since
there is no need to support this chipset, this change will revert all
HSCL functionality to remove any confusion.
This reverts commit 13f08126290f40aae7476bfe8c374459f0fcd041.
Change-Id: Ia14b89faed2a3285b5ef5af6d16ebf225ffa4cda
Signed-off-by: Benet Clark <benetc@codeaurora.org>
IGC(Inverse gamma correction) feature is supported on source side pipes
in MDP. Clients of MDP driver can enable the feature using overlay ioctl
interface. Change adds support for clients of driver to enable the
feature.
Change-Id: I5243b001acffff869f9369211fd724d7dd75e8a1
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
For source pipes post processing feature params are cached in the pipe
structure. Post processing(pp) feature versions can change across
different versions of mdp and might require changes to caching code.
Post processing driver can handle caching the params based on version.
This change moves the caching into post processing driver
Change-Id: Ic02fec43dbbff5d4404b618d6d82b2c8b8eef07a
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Updated the HDMI driver to conform to new 2.0 specification. Updated EDID
parser to handle new data blocks defined in CEA-861-F and added support for
yuv420 output format type.
Change-Id: Ia424c13c585e7f3a9b572a472a997c13aa7e3c0f
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
User-space decides how many layers to send for MDP composition using
max blending stage value passed by the driver. Currently driver sends
this value based on its internal enum value which does not reflect the
correct number of blending stages that HW supports. So user-space makes
independent assumption to derive at correct value by deducting 2. This
is incorrect design and may lead to unforeseen issues. Fix it by sending
correct max blending stage value.
Change-Id: Iaaed7b6824e6ef445ca202fb993d1061811b5ce0
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Starting MDSS 1.5, display controller can blend 7 layers excluding
base layer. If a pipe is staged on stage6, it requires use of extension
register. Current logic has a bug where if VIG3 of RGB3 pipes are on
stage6 then configuration is incorrect and leads to bad HW behaviour.
Fix this by correcting the staging logic.
Change-Id: I4f34783a9bd8ae5e0898bcf25755cf687f195211
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
MDP block supports picture adjustment feature on the DSPP which can be
enabled/disabled by driver clients. Change adds the support in post
processing driver and allows clients of driver to configure the PA block
in DSPP.
Change-Id: I22e3df32fd67fda4029eeb4740ad47917ae7e3a1
Signed-off-by: Benet Clark <benetc@codeaurora.org>
The PP cache currently stores the 'data' structure for PAv2. For newer
MDP targets, the PP res cache needs to store the PAv2 config data
structure, which has some PAv2 configuration info as well as the 'data'
structure nested inside. The configuration structure is needed in the
cache because it contains info for newer targets required when updating
the registers.
Change-Id: Idd1aa23687245ab7cc71c2c7a9cb74958c77dcec
Signed-off-by: Benet Clark <benetc@codeaurora.org>
At cmd_stop, spin lock protection is necessary when reset rdptr_enabled
to 1. Otherwise race condition may happen and cause timeout.
CRs-Fixed: 766216
Change-Id: I128f73a069d3068c852f4b25c6515ec834e82162
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Rotator is a non real time client. Limiting the read and
write transactions can help preventing peaks in the bandwidth
required by the rotator client.
Change-Id: I479706598827236daa82a7f42924ecafd37724b8
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
While using simulator panels through debugfs, all the necessary
parameters are updated except panel_max_vtotal. This parameter is used
to derive bandwidth and mdp clock rate for video mode panels. So if this
parameter is not updated while switching simulator panel from low to high
resolution then we are under voting and under clocking MDP. This leads to
under-runs. Fix this by updating panel_max_vtotal with latest v_total.
Change-Id: Ia51340c597e8234d59660b43f19a841ffb96dad3
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Default the pinctrl state to NULL before selecting
a pinctrl state. This ensures that IS_ERR_OR_NULL
called on the variable will return true.
Change-Id: I3e798cade45f4ef4179b1883e2eb33c3fd7d851f
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
MDP block supports histogram feature in DSPPs which can be enabled
or disabled by driver clients. This change adds the support in
post-processing driver to allow histogram configuration in DSPPs.
Change-Id: Ib8cdf83f557c1a44304bc168187ca826486cdc3d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Add systrace events to log the time to process a blank
request; this helps to profile the time that display
driver takes during the power transitions.
Change-Id: I0081c3825a4776561db248123d701c25101e9245
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
In order to successfully halt vbif client, need to ensure that client
core clock is on while halting and waiting acknowledge of vbif halt.
Change-Id: I9f17e90f34cf4b3033bc4f3b23e2c1df8fc3aa69
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
While refactoring VBIF registers programming
(commit 41efd125ffe5403698155043073dd826abc534cf)
software reset programming was switched from using
mdp based to vbif base, this is incorrect programming
and software reset wouldn't work in case hardware
behaves incorrectly.
Change-Id: I8738bc4fc96ec8ba7130a891231c34bd4ce10449
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Reading the default panic LUTs after disabling the splash clks in mdp
probe when continuous splash is disabled in lk causes the crash. This
change disables the splash clks after reading the panic LUTs.
Change-Id: I8fc4ed0f515a3b657a40cd430150353ffb90db35
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Reduce vsync waiting time only when vsync is still enabled.
Otherwise, it will trigger waiting for next vsync mistakenly
and timeout eventually.
CRs-Fixed: 762791
Change-Id: Ic3df12a4b449fa6d6cbbd1169e890b0cf3f67db1
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Frame buffer memory could still be fetched until panel is completely
blanked, in order to avoid potential page faults by unmapping early,
move unmapping of this memory until after panel is blanked.
CRs-Fixed: 763046
Change-Id: Ib7eea73a7549b453cf2fc31a31f5cc3e9e1cce39
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
During high performance scenarios, sometimes the DSI RDBK registers
are not getting cleared. This can cause improper read return values
since the RDBK data count will not get reset in such cases. Add
memory barriers during reset of RDBK registers to ensure that
the registers are cleared.
Change-Id: I870744b58c3e4064ca9f04f92e831d69139336db
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
The use of bl_lock is to protect backlight related resources, however by
holding it during display thread shutdown it may lead to deadlock if the
same is being acquired inside display thread. Reduce the scope of the
lock to just the backlight resources to prevent deadlock.
Change-Id: I6e4b9a970c4a5a050caab1b3714e90eda107edee
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
