Update TDM slot mapping and add hostless FE DAIs for customized
sound card on automotive platform.
CRs-fixed: 2024584
Change-Id: I08c2765972405e6dfbbcd6d2590109e119b92423
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add route from QUAT_TDM_TX_0 to AUX_PCM_RX Port Mixer and route from
INTHFP_DL_HL to AUX_PCM_RX.
CRs-fixed: 2024590
Change-Id: I395808fe9937128f0391668132a4dffdb6c60f42
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add the CPU and GPU clock FMAX tables for the MSM8996 Pro
auto target.
Change-Id: If655756b4598c20e85fd73720073b7d16ce143e9
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Adding iommu fault handler callback to iommu driver, which will be
called when memory fault happens.
Change-Id: Ia2486fe167b889633ea4fb4c42601791efda133c
Signed-off-by: Yajun Li <yajunl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Kernel DRM SDE driver doesn't know the alignment requirement from
user space, so it needs to be updated when pitches value when
they are different than fb value.
Change-Id: I392e247330980fcac87b6fbe49a289e0fc473d85
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
When multiple bridge chips are connected to same interface, the
drm mode in the mode_set has combined timing parameters. For
each individual bridge chip, those timing parameters need to
be divided by panel count.
CRs-Fixed: 1085590
Change-Id: I9af0fa99ab6bcf9e09f4f7b372d53e6f1638e6d0
Signed-off-by: Jin Li <jinl@codeaurora.org>
Add ADV7533 node into DRM display manager node to enable this
bridge chip on MSM8996 Auto Agave platform.
Change-Id: Ia430a14f8810d7db25f2f62104416c0d063a9ee5
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Include and refine sde display device tree to make drm kms
initialized successfully on MSM8996 Auto Agave platform.
Change-Id: Ifcf23f04710fb855c51b3e4e2a8b872ba8dec7c3
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Add support for 7 channel mapping in asm to support
7 channel playback.
CRs-Fixed: 1114041
Change-Id: I0daf306d4495d3966406d05fc6328b2956a2d11f
Signed-off-by: Rohit Kumar <rohitkr@codeaurora.org>
Power and perf clusters early boot up frequencies require to be
updated to maximum frequnecy of NOM voltage corner to improve
the boot up time, so add support for the same.
Change-Id: Icf54a648f47765867812edc5a68cf52b7fd58fdd
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
for boot optimisation remove synaptics and nfc device
support on automotive platform.
CRs-Fixed: 1002431
Change-Id: I324acdc51dd915069233feeb5710cb45a548c769
Signed-off-by: Atul Raut <araut@codeaurora.org>
Allow compilation when CONFIG_ARM_SMMU is not selected by making
CONFIG_IOMMU_IO_PGTABLE_FAST depends on CONFIG_ARM64_DMA_USE_IOMMU.
Removed inclusion of dma-mapping-fast.h by dma-iommu.h.
CRs-Fixed: 2000526
Change-Id: Iadfc236f848f46e6742a98581dbfdb13c7a2695e
Signed-off-by: Atul Raut <araut@codeaurora.org>
if !CONFIG_DMA_CMA throws error implicit declaration of function
‘dma_contiguous_early_fixup’ in routine
drivers/base/dma-removed.c:removed_dma_setup which has no
dependency over CONFIG_DMA_CMA.
Fix by removing dependency of CONFIG_DMA_CMA flag
for function dma_contiguous_early_fixup
CRs-Fixed: 1117213
Change-Id: Ife6d0399b7ae61d1781212a1ae7525378fb920fc
Signed-off-by: Atul Raut <araut@codeaurora.org>
The clock driver sets the sleep_ena bit to allow the hmss_ahb_clk
to be disabled by hardware during certain low power modes. The
PCIe controller however might need to access some registers that
need this hmss_ahb_clk to be on. Remove the additional settings
in the clock driver to resolve the issue.
CRs-Fixed: 994609
Change-Id: Ib486a27f2e1c2d2231f8bedcb4ee8b39381cbd25
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This reverts commit e15b1696c1
which is introducing a change to defconfig (CONFIG_MSM_L2_SPM)
that is not defined in any Kconfig file
Change-Id: I4f63048880b6f4f1f840ad973686d7ff1f9cc062
Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
As per the hardware characterization, update open loop voltage
adjustment for graphics CPR regulator on msm8996pro automotive
SOC.
Change-Id: Iae38ac2d1dd30b73fead14efa27e72c6110a2f78
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
As per the hardware documentation, update the regulator
configuration for apc0, apc1, gfx CPR regulators to support new
speed bins in msm8996proAU.
Change-Id: I140cec39460975f6e95738322259f6a924a26a74
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Check for legacy PM4 commands instead of adreno version to calculate
ringbuffer space for PM4 commands that write to memory.
Change-Id: I5d1d4cfbc70bc73ddee9ee752de24aae154a04dc
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
As per the hardware documentation, update the APCC CPR controller
and regulator configurations for msm8996pro automotive SOC. This
includes disabling closed loop operation for APCC CPR and
adjusting the regulator configurations for APC0, APC1 and
APC_CBF.
Also, update the CPR configurations to support speed bin 0 only
for APCC CPR regulators on 8996pro automotive SOC.
CRs-Fixed: 1039626
Change-Id: I2eba3807aa14ca7a3a52b18866758e86eb921600
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Set the CPR IRQ affinity of the VDD_APCC CPR3 controller to be
both cores of the APPS power cluster (i.e. CPU0 and CPU1). This
ensures that neither of the CPU cores of the performance cluster
will be woken up to service a VDD_APCC CPR IRQ which was
generated when the last performance cluster core power collapsed.
Change-Id: I055e50ffcb85622ddd67d55b44d77c342e9ec074
CRs-Fixed: 949650
Signed-off-by: David Collins <collinsd@codeaurora.org>
Hardware characterization has shown that the CPU LDOs can
operate safely with less than 150 mV of headroom voltage.
Reduce the CPU LDO minimum allowed headroom voltage for both the
power cluster and the performance cluster in order to save power
by allowing LDO usage in more situations.
Change-Id: I72f28569d4719540fc84cf65d8783bbfec9435ad
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
