Add support for controlling the multimedia clocks on
MSMCOBALT v2.
CRs-Fixed: 1015446
Change-Id: I636001ea91e7be1e2adec2ea7cd3d9aadfcc39a2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Change-Id: I559f5976b56bf8933df2c68fc4e29b2bd0ce1160
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This change provides the below updates:
- Current DP PLL driver uses the pll_base and the base
address for the TXn registers instead of phy_base address.
Fix this by using the correct base address.
- Disable handoff for vco_divided_clk
by implementing handoff function for this clock.
- Update the PLL settings to fix PLL locking issues.
CRs-Fixed: 1009740
Change-Id: Iea46c5b0482bceb841309175ede42ec3be3e20fd
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
The DP link clock path in the DSI PLL has a mux clock (dp_link_2x_clk_mux)
which allows the pixel clock to be either sourced out two divider clocks.
In the current code, the ops for this mux clock is overloaded
incorrectly which results in the link clock being always sourced
out of the first divider clock. Fix this by using
the default mux clock ops for this clock.
CRs-Fixed: 1009740
Change-Id: Ie12d5ab272dbd79fe97225864c2360fdde7325a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
The video subcore RCGs should be force enabled during rate
scaling to workaround video firmware potentially disabling
the branch clock at the same time on MSMCOBALT.
CRs-Fixed: 1020896
Change-Id: I45a119591efc36fa05ee7009d938e596b015e70c
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Make sure that the RCG parents are turned on before force enabling
it and changing its configuration.
CRs-Fixed: 1020896
Change-Id: Ia633c4dcbab62fc6a4407c5896e36a7bbef48579
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
VCO configuration should be based on the requested vco
clock rate and should not factor in the bit clock source
divider. In addition, the bit clock source divider for
the slave controller should always be set to 1. This will
ensure that the PLL is locked at the correct rate.
CRs-Fixed: 1019289
Change-Id: Ie5c171e13dcccc711ba03acb38fcd7876e792cee
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Correct the sequence to turn on the GPU_GX gdsc as part of
enabling the GFX CRC.
CRs-Fixed: 1018785
Change-Id: I64d0abe7091f81f85e83747f09ece4bc524a4057
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for controlling the peripheral clocks on
MSMCOBALT v2.
CRs-Fixed: 1015446
Change-Id: If69f3752c4295f4cc49cf41854edc03aa90dbbc5
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
For the fabia PLL to be in STANDBY mode, the RESET_N bit should
be set so that the PLL comes out of reset. Else, the PLL is
at OFF state and changing it's frequencies would not cause the
ACK_LATCH to be set.
CRs-Fixed: 1018752
Change-Id: I30f1ee0f4fdb8d92a9f6e187c1d8b797a0bdc94d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Implement clk_osm_get_cpu_cycle_counter() which returns the
running cycle counter value. Register these two functions with
a scheduler-provided callback to allow the scheduler to estimate
CPU frequency without notification. Lastly, setup the cycle
counter to be increased on every rising edge of the XO clock
for improved accuracy.
Change-Id: Ie0f60ca79efc05901a88da13f7a6476f390518a5
CRs-Fixed: 988356
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
When SPM_CORE_RET_MAPPING is set to 1, cores in retention
are treated as inactive by the OSM. However, currently
this register is programmed to 0 when the flag to treat
cores in retention as inactive is specified. Fix this.
Change-Id: Ibc5df71ddd0cfdabf82d3c1e47efca0d88823a2f
CRs-Fixed: 1017123
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add programming the PLL_CAL_L_VAL register to the fabia PLL
set_rate sequence. This is required on MSMCOBALT v1 as a
workaround.
CRs-Fixed: 1016938
Change-Id: I298acf633228b2c565736bf7bfd446d96f4e1983
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux)
which allows the pixel clock to be either sourced out of the VCO clock
or the bitclock. In the current code, the ops for this mux clock is
overloaded incorrectly which results in the pixel clock being always
sourced out of the bit clock. Fix this by using the default mux clock
ops for this clock.
Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The pcie_aux_clk_src needs to run at XO frequency instead
of at 1MHz. Update the clock driver to support that.
CRs-Fixed: 1013278
Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Program the PLL test control register for the power
cluster clock in agreement with hardware guidelines.
Change-Id: I102fd544ea0571d31d2ef9232195d4adbddda6d7
CRs-Fixed: 1009203
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The hmss_gpll0_clk_src RCG only needs an SVS2 vote on CX
to run. Update the FMAXes in the linux clock driver.
CRs-Fixed: 1013237
Change-Id: I31aaeb7cf965bfbee4aa219936d8e298899b61a8
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream.
The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c upstream.
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
(show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
(dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
(time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
(start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c43 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream.
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit bb473593c8099302bfd7befc23de67df907e3a99 upstream.
As preparation for arm64 based mesongxbb, which pulls in this code once
enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch.
The loop uses a local unsigned int variable, so adopt that type,
matching the header.
Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 50359819794b4a16ae35051cd80f2dab025f6019 upstream.
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.
On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.
To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.
The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.
Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add new UFS clocks to support enabling/disabling the hardware
dynamic gating for their corresponding branch clocks.
CRs-Fixed: 1012355
Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add a new hw_ctl_clk type to allow clock clients to enable
hardware dynamic gating of the clock branch.
Clients should use the clk_enable API on a separate hw_ctl_clk
clock structure to set this bit. Vice-versa for clearing it.
It is mandatory that the clients call clk_enable on the actual
branch clock before enabling the hw_ctl_clk clock.
CRs-Fixed: 1012355
Change-Id: I24e78353fa07f537bafc322dba6b1ffac913cd1d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
To ensure stable operation, it is necessary to place LMh SW override
votes when setting the new rate of the power and performance
CPU clocks. Add support for parsing these values from Device Tree
and programming them in clk_set_rate().
Change-Id: I60d90d546f155edb6c13c46e6c59c75e95848d6c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for new Display-port PLL clock driver to handle
different DP panel resolutions in msmcobalt. Add separate files
to support this new PHY PLL block.
CRs-Fixed: 1009740
Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add programming support for the qspi_ref and qspi_ahb clocks
in the linux clocks driver.
CRs-Fixed: 1011840
Change-Id: Ic67b72b1e9341fec33bcdbde67f9e2c7e8045ec1
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
OSM clock period is 5 ns. Therefore, the various hysteresis
timers used by OSM can be fine tuned with a granularity of
5 ns. Allow specification of timers in units of nanoseconds
to prevent losing valid timer setpoints.
Change-Id: Ice93347aaf81fe41ea7862752ac0d2d4e82d838c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Increase the refcount of CPU clocks proportionally to the number
of available CPUs to maintain the assumption that each CPU clock
has been prepared and enabled by the time cpufreq takes over.
Change-Id: Icccb28bc7a88dc76cf4ed5710623e992ba62f19c
CRs-Fixed: 994035
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add SVS2 frequencies to the ufs_axi_clk_src and
ufs_ice_core_clk_src clock sources on MSMCOBALT.
CRs-Fixed: 1010329
Change-Id: I01210f48d32d7d6cb32f4977e52fb46acd33b1ba
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add the BCR register for the gcc_ufs_axi_clk and
gcc_blsp1/2_ahb_clk clocks.
CRs-Fixed: 1005036
Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for controlling the graphics clocks on
MSMHAMSTER.
CRs-Fixed: 1004885
Change-Id: If96d8e7e0cd97cf45c48c6c39236d42659e25ea2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for controlling the multimedia clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: Ic995c37ae819ce16668374cecf28fa98e6cf3180
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for controlling the peripheral clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the FMAXes for some camera clocks to align with
their supported frequencies.
CRs-Fixed: 1007250
Change-Id: I5691c34376f54845cbd288bb824d67fb1b8e4bbc
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The OSM clock is sourced from the LMh RCG. Model this RCG so
that it can be configured properly to provide the OSM a 200 MHz
clock source.
Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc
CRs-Fixed: 1007896
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support to program the DSI PLL on msmcobalt which is needed to drive
the DSI byte and pixel clocks.
CRs-Fixed: 1000576
Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
The hmss_gpll0_clk_src is being sourced off the gpll0 which
uses the cxo_clk_src RPM resource. This causes XO shutdown
to fail. Use the gpll0_ao source instead.
The hmss_ahb_clk_src RCG frequency table is also updated to
use the cxo_clk_src_ao to generate XO frequency.
CRs-Fixed: 1001330
Change-Id: Ic5cba530ea22cd19a20a21f0c33433c5e023debc
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The glm clocks are controlled by TZ, so remove support for
these clocks from the clock-gcc-cobalt driver.
Change-Id: Ibfb8f211ca8c29617aca4ff0ee885366f95aac00
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Change the log about the clocks being enabled even without a
SW vote to pr_warn instead of WARN. The stack trace isn't very
helpful in this case and cause a lot of logging.
Also, add the check_enable_bit property to some SMMU clocks
which are votable.
CRs-Fixed: 1006841
Change-Id: Icb15b038b170590e69073ca628b3d610e14893da
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The throttle clocks are managed by XBL and HLOS does not need to
control them. Remove support for these clocks from the clock
driver.
CRs-Fixed: 1006824
Change-Id: I1a33b3dbde6d5526be1073874e28b12350adad5e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
clk_get_sys was updated to return EPROBE_DEFER because on the
older kernel returning ENOENT was causing drivers that probed
before the clock provider to fail instead of deferring. The new
kernel version fixes this by returning EPROBE_DEFER in
__of_clk_get_from_provider. Thus, clk_get_sys failing means that
the clock provider exists, but the requested clock is not defined
in the provider, in which case ENOENT is a more appropriate error
code to return.
Change-Id: I67d60bf5c0d2dfb71a189e351bc5b4c535d280bb
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Add HW clock measurement support for the gcc_gpu_cfg_ahb_clk,
gcc_gpu_bimc_gfx_src_clk and gcc_gpu_bimc_gfx_clk clocks.
CRs-Fixed: 1003179
Change-Id: Id403238f612a277973cd06f7d1d6f656a1812bba
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
There is a configurable divider between the byte_clk_src RCGs
and the mmss_mdss_byte_intf_clk clocks. Add support to program
it.
CRs-Fixed: 1003173
Change-Id: I976c2b9e9739b603f6cfb10d11c7b1d64cb577c5
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The CPR driver on MSMCOBALT needs the gpucc_rbcpr_clk clock in
order to probe and register the gfx_vreg regulator which the
graphics clock driver in-turn is dependent on for registering
the gfx3d clocks.
To break this circular dependency, register the non-gfx clocks
first, let the CPR driver probe, and then register the GPU PLLs
and gfx3d clocks. Also, correct the gfx CRC sequence.
CRs-Fixed: 986619
Change-Id: Id16ad7940e96cc9d5a3127551c8a92b05cfbb181
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream.
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.
Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit e8b63288b37dbb8457b510c9d96f6006da4653f6 upstream.
hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.
Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
