This reverts commit 8125696991.
The commit"cfg80211/mac80211: disconnect on suspend" forces disconnection
on wlan interfaces if wake on wireless is not enabled from the user space.
Wake on Wireless is enabled by default in wlan driver (CLD) and cfg80211
layer never aware of wake on wirless enabled status done in wlan driver.
To avoid the disconnection while going to suspend and keep wlan driver
in WOW mode by default, the commit "cfg80211/mac80211: disconnect on
suspend" should be reverted.
CRs-Fixed: 540571
Change-Id: I483fe0530f9f00c338680416449215af326e3df1
Signed-off-by: Ganesh Kondabattini <ganeshk@codeaurora.org>
This reverts commit f04c22033c.
The commit "cfg80211: export interface stopping function" exports a new
cfg80211_stop_iface() function, intended for driver internal interface
combination management and channel switching. The new function is used
by commit "cfg80211/mac80211: disconnect on suspend" which is reverted
in order to avoid the disconnection while going to suspend. Hence the
commit "cfg80211: export interface stopping function" should be reverted.
CRs-Fixed: 540571
Signed-off-by: Ahmad Kholaif <akholaif@codeaurora.org>
AP stopped interface can be used to indicate that the AP mode has
stopped functioning, WLAN driver may have encountered errors that has
forced the driver to stop the AP mode.
When the driver is in P2P-Go mode, and when it goes thru automatic
recovery from firmware crashes, it uses this interface to notify the
userspace that the group has been deleted.
CRs-Fixed: 453060
Change-Id: Ifcd8d4f0c0b26f56a56fb8560aa474297b7521d4
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
When flag WIPHY_FLAG_DFS_OFFLOAD is defined, the driver would handle
all the DFS related operations. Therefore the kernel needs to ignore
the DFS state that it uses to block the userspace calls to the driver
through cfg80211 APIs. Also it should treat the userspace calls to
start radar detection as a no-op.
Change-Id: I9dd2076945581ca67e54dfc96dd3dbc526c6f0a2
CRs-Fixed: 630797
Signed-off-by: Amar Singhal <asinghal@codeaurora.org>
[neelanshm@codeaurora.org: Do not include the unrequired
change in util.c]
Signed-off-by: Neelansh Mittal <neelanshm@codeaurora.org>
This commit merges the following commits into one snapshot up to
msm-3.18 commit e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1.
8e465d5 msm: wlan: Update tx power limits of country UA
296bec0 msm: wlan: Update regulatory database for some countries
c0fc361 msm: wlan: Fix the DFS region for Japan
6f1cca3 msm: wlan: Update the wifi regulatory database for TW
2c5867a msm: wlan: Modify JAPAN regulatory rules
e430543 regdb: Update database with 60GHz for Japan
ccce8fb msm: wlan: Correct the parsing of db.txt
acf74a2 cfg80211: add space after the b/w in db.txt
b2b5b4e msm: wlan: update the dfs_region to db.txt
36c64bd msm: wlan: Add country KP
da5d9cb msm: wlan: Update db.txt for regulatory support.
Signed-off-by: Ryan Hsu <ryanhsu@codeaurora.org>
Taking the gratuitous ARP/unsolicited NA detection code from
mwifiex (but fixing it up to not have read-after-skb-end bugs),
implement the ability for userspace to request the behaviour
required by HS2.0 to drop gratuitous ARP and unsolicited NA
frames when proxy ARP service is enabled on the AP. Since this
behaviour is only mandatory for HS2.0 and may not always be
desired, make it optional - modify cfg80211/nl80211 for that.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: be9efdecf8ecdcc6d2221845482e7359b33a603b
Git-repo : git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
Change-Id: I1e4083a2327c121073226aa6b75bb6b5b97cec00
CRs-fixed: 621827
[akholaif@codeaurora.org: only picked up the declaration
and definition of cfg80211_is_gratuitous_arp_unsolicited_na()]
Signed-off-by: Ahmad Kholaif <akholaif@codeaurora.org>
This is to help the hardware configured in world
roaming mode to save power when not connected to
any AP.
CRs-Fixed: 542802
Change-Id: Ia643d0e9848dcd486832973bd6dd186edd7bd4ea
Signed-off-by: Mihir Shete <smihir@codeaurora.org>
Add new flag WIPHY_FLAG_DFS_OFFLOAD to the wiphy structure. When this
flag is defined, the driver would handle all the DFS related operations.
CRs-Fixed: 630797
Change-Id: I592722607788dc4e2167c90bb684071cc9fb6986
Signed-off-by: Amar Singhal <asinghal@codeaurora.org>
This is a snapshot of the icnss driver and associated files as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of kernel.lnx.
3.18-151201.)
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This is a snapshot of the cnss driver and associated files as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of kernel.lnx.
3.18-151201.)
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This is a snapshot of the cnss prealloc driver and associated files
as of msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of kernel.lnx.
3.18-151201.)
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This is a snapshot of the wcnss driver and associated files as of
msm-3.18 commit:
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of kernel.lnx.
3.18-151201.)
Signed-off-by: Yue Ma <yuem@codeaurora.org>
The TYPE for a PMIC chip is always 0x51. There is no need to define it
for each PMIC chip.
Also the SUBTYPE of a PMIC chip doesn't change with versions. Have a
single definition of the SUBTYPE per PMIC chip.
Also, the driver uses integer indexes to get to the pmic name, instead
use the SUBTYPE to index in the pmic names array.
Change-Id: Ie1c43f3db0d4a395307253aad347ad93624a1203
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
An earlier commit 52a3101ed9b61787a49f3b5c298aa9240f4006dd
added a recursive dependency as part of CONFIG_DEBUG_SPINLOCK
lib/Kconfig.debug:585:error: recursive dependency detected!
lib/Kconfig.debug:585:symbol DEBUG_SPINLOCK_BITE_ON_BUG depends on DEBUG_SPINLOCK_PANIC_ON_BUG
lib/Kconfig.debug:593:symbol DEBUG_SPINLOCK_PANIC_ON_BUG depends on DEBUG_SPINLOCK_BITE_ON_BUG
Fix this by adding a choice menu.
Change-Id: I0e50103397bb71dec7056db5148cba988550b860
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Software running in non secure EL1(on arm64) and non secure
supervisor mode(on arm) should use virtual timer for time
stamping. Migrate users to arch_get_cnt_vct instead of using
arch_get_cnt_pct.
Change-Id: Ic3cf52a2ca3b0a2f83b926df26cecf479080320c
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable support for esoc interface layer with external
soc components on the msm debug and perf defconfigs.
Change-Id: I33a4b1f8cdda9a287e6715b23da8b3876abc2ab0
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable triggering wdog on kernel panic and enable panic
on data corruption.
Change-Id: I4798ff27ef470225607fdccc15e8fa3a6ebdb1eb
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Disable SPI on msmcortex debug and perf configs
since it fails to compile.
Change-Id: Ia9e4077428a0760f1428b81597503e92402bad2a
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
As per ARM the prefetch for store (prfm pstl1strm) in the arch_spin_trylock
routine can lead to some false positives, decreasing the lock performance.
On the Cortex-A57 / Cortex-A53, if the memory type is Shareable, then any
linefill started by a PST (prefetch for store)/PLDW instruction also causes
the data to be invalidated in other cores, so that the line is ready for
writing. This will also clear the exclusive marker associated with that
cache line (clearing the exclusive monitors).
So, in the scenario where we could have multiple cores trying to acquire
exclusive access to a cacheline, the removal of prefetch would help with
potentially increasing the chances of one of the cores making progress.
Example:
struct {
spinlock_t lock;
atomic_t count;
} x;
We have 2 cores trying to run the below code
spin_lock(&x.lock);
atomic_inc(&x.count);
spin_unlock(&x.lock);
lock and count are part of a struct so they fall into the same cacheline.
The lock function uses the trylock mechanism as part of debug spinlock.
1. Core1 has acquired the spinlock and is performing the ldxr, add, strx
loop in atomic_inc.
2. Core2 are trying to acquire the spinlock.
Core1 | Core2
ldxr | |
| | prfm pstl1strm
add | |
| | ldaxr
stxr (fails) | |
| |
Now, the prfm always clears the exclusive marker for the core1 ldxr,
so the stxr always fails. This prevents core1 from making progress and
releasing the spinlock that core2 is waiting for.
This could potentially go on forever and we end up breaking this pattern
if the timing changes or if an interrupt triggers.
This could happen with more cores trying to acquire the spinlock, cause
more prefetches and make the problem worse.
By removing the prfm, we allow the stxr @core1 to suceed and atomic_inc
completes, allowing core1 to unlock the spinlock and let core2 proceed.
Change-Id: I742ab9b6d98aded628e4dcf4a6ec68b8e2a4ec3e
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[abhimany: resolve minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Currently dump_stack is printed once a spin_bug is detected for rwlock.
So provide an options to trigger a panic or watchdog bite for debugging
rwlock magic corruptions and lockups.
Change-Id: I20807e8eceb8b81635e58701d1f9f9bd36ab5877
[abhimany: replace msm with qcom]
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Currently we cause a BUG_ON once a spin_bug is detected, but
that causes a whole lot of processing and the other CPUs would
have proceeded to perform other actions and the state of the system
is moved by the time we can analyze it.
Provide an option to trigger a watchdog bite instead so that we
can get the traces as close to the issue as possible.
Change-Id: Ic8d692ebd02c6940a3b4e5798463744db20b0026
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Once a spinlock lockup is detected on a CPU, we invoke a Kernel Panic.
During the panic handling, we might see more instances of spinlock
lockup from other CPUs. This causes the dmesg to be cluttered and makes
it cumbersome to detect what exactly happened.
Call spin_bug instead of calling spin_dump directly.
Change-Id: I57857a991345a8dac3cd952463d05129145867a8
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Data corruptions in the kernel often end up in system crashes that
are easier to debug closer to the time of detection. Specifically,
if we do not panic immediately after lock or list corruptions have been
detected, the problem context is lost in the ensuing system mayhem.
Add support for allowing system crash immediately after such corruptions
are detected. The CONFIG option controls the enabling/disabling of the
feature.
Change-Id: I9b2eb62da506a13007acff63e85e9515145909ff
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[abhimany: minor merge conflict resolution]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Enable the error detection and correction driver for
L1/L2 caches on the ARM Cortex-A cpu clusters.
Change-Id: I8dc9e3719ae9868aaee51ef2186e513a3da1a4f7
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Snapshot cortex-a arm cpu edac driver from msm-3.18@
0922caf50f22e751a05e6d613bb1d0c1dc940d7d
("Merge "usb: dwc3-msm: Fix incorrect roles with
multiple instances")
Also fix up ESR macro usage to follow upstream norms.
Change-Id: Ic5498a1ebc9c9d402baf4b839ed8f427e9510083
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
EDAC provides a mechanism to poll for errors using a callback function
and uses a delayed timer to schedule it. Provide an option to create
a deferrable timer if the error checking is not worth waking up
the cpu from idle.
Change-Id: Ia25216323eabf7fa4b894897c950414006921f3f
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add an EDAC device flag and associated sysfs entries to
allow an EDAC driver to be configured to panic the kernel
if a correctable error is detected. Though correctable
errors (by definition) have no adverse system effects,
a panic may still be useful, since a correctable error may
be indicative of a marginal system state.
Change-Id: I98921469254aa7b999979c1c7d9186286f982a0c
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Add a macro containing the MIDR Primary Part Number value
needed to identify ARM Cortex A72 processors.
Change-Id: I6a0d04930070523c3dba83f3d7869ba75288b531
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
[abhimany: resolve minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Move SCSR register offsets and bit positions specific to SPSS from
driver to device tree entry.
CRs-Fixed: 972423
Change-Id: I9712cc550b858af54c90ae92c8636e1d37b3f993
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
Read back value of QDSP6SS_MEM_PWR_CTL after writing, to comply with
reset sequence specification.
Change-Id: Ib803656355c4d498c83fe5cd017823afc5db2c60
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Update the reset sequence to read and override acc register based on msm
specific value provided in device tree.
Change-Id: I8ed290f5ab5e48e94ef5c8c91fd1d8f8414e86f7
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
This patch adds the code to handle watchdog, err_ready and other
interrupts from secure processor subsystem to the PIL driver.
CRs-Fixed: 972423
Change-Id: I65455229ee14bd4da357358ac3977f2137f3c07e
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
One possible cause of a system error exception is an ECC
error in the CPU's caches. Call the ARM64 EDAC error
handler from the system error exception handler to print
EDAC error syndrome information to the kernel log.
Change-Id: If8757eda0c7fc82b0fccee573cf09627a752fdf3
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[satyap: replace ESR_EL1_* with ESR_ELx_* to align with kernel 4.4]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
LPM modes can fail if there is a pending IPI interrupt at GIC CPU
interface. On some usecases frequent failure of LPM modes can
cause power and performance degradation. Hence, prevent cluster
low power modes when there is a pending IPI on cluster CPUs.
Change-Id: Id8a0ac24e4867ef824e0a6f11d989f1e1a2b0e93
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Update the regulator API used in PCIe endpoint driver for 4.4
kernel upgrade.
Change-Id: Iacca851bfbd7f5a5544b97ac82630d9a2dc5ebfc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support of PCIe Endpoint (EP) mode for mdmcalifornium.
Change-Id: I55c85813e674810d865b444b7e19ce4157cea479
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update check for valid MSI enable and setting using
MSI_ENABLE bit instead of address and data. Host can
set address and data to 0 therefore check if MSI_ENABLE
is set.
Change-Id: I686c3ed155b8c5c843d12a49218f4720655dcc18
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Update the configuration of PCIe PHY based on the version of PHY.
Change-Id: I1faf65c2cc1215cd6ad679d0c4558a17f43db3fc
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the support to trigger link training based on PCIe PHY version.
Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
Add the phy reset clock for PCIe endpoint mode and add the support
of this optional clock.
Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777
Signed-off-by: Yan He <yanhe@codeaurora.org>
PCIe device ID can't be got from register when the power of the
core is off. Thus, use the saved device ID so that we can turn on
link in the debugfs testing.
Change-Id: I28ec17b4fdf84b130cd32267d097b1c0d7c32aed
Signed-off-by: Yan He <yanhe@codeaurora.org>
Fix the bug of the power status of PCIe core and update the power
status as soon as power is turned on.
Change-Id: Ib5b550c78a630d36049296daf1291065a1a44cd5
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.
Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update the lpeak values of PCIe LDOs based on the updated HW
requirement.
Change-Id: I2f8b63edf3f8571ea960abdebde982324f7f6d74
Signed-off-by: Yan He <yanhe@codeaurora.org>
Update some read-only PCIe registers with non-arbitrary values
which are required by PCIe compliance testing.
Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4
Signed-off-by: Yan He <yanhe@codeaurora.org>
The logging macro has multiple outputs. If we increase the counter
as a parameter to the logging macro, the counter will be increased
for multiple times. The change here fixes this bug.
Change-Id: I321e281b506e35770e222def86f5b04ae0bfdce2
Signed-off-by: Yan He <yanhe@codeaurora.org>
