Current driver code doesn't handle the memory allocation failure
correctly and ends up leaking memory and trying to free
unallocated one.
Change-Id: I7e3527b7e08ccfe566d85e3009d8a015d8daa707
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Error handling check added in probe function and
memory cleanup in remove function.
Change-Id: Ic8f02dcc89e716ec88b711496d1e43754b95968d
Signed-off-by: Gaurav Singhal <gsinghal@codeaurora.org>
In vfe 48 version the stats write masters have to be enabled
in addition to enabling the stats module. Add code to do this.
Also, the stop of write master was not programmed correctly, fix
this.
CRs-Fixed: 999619
Change-Id: Ic5b38b038508802b0b5779dc5d54ec6772f24b65
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Add a new voting path to IPA bus scaling from master CPU
to slave IPA_CFG. This is needed in order to achieve peak
throughput on SW bridge path.
CRs-Fixed: 983795
Change-Id: I25a00441f91087a370764b451ecc73a49a75b0a6
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Comments for ufshcd_quirk_tune_host_pa_tactivate() function doesn't
match the purpose of it. This change fixes the comments to describe
what function is actually doing.
Change-Id: I462a750aa6ee69f588b4bbcf5cb030f9e7292951
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add napi framework to use napi API's to poll
embedded data from IPA HW.
Change-Id: Icb6ec9d060ca4fb02e95c1e98bded89422bb1fff
CRs-Fixed: 1002026
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Support using 7 bits in the SOFT_RB_SPARE PON register if the
PON peripheral is GEN2, otherwise use only 6 bits. This allows
compatibility with bootloader code on targets with older PMICs
where 7 bits for restart reasons are not necessary.
Change-Id: Ibf7fc53d3ff7084b252a44c44e3ce29326659787
CRs-Fixed: 1023239
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
There is a race condition between setting PD_ACTIVE = 0 and when losing CC.
If PD_ACTIVE is not set to 0 by the time the TYPE_C interrupt fires on
disconnect then the POWER_SUPPLY_TYPE will not be set to UNKNOWN.
Instead of relying on PD_ACTIVE being set to 0 before the TYPE_C interrupt
fires, just update the type upon PD_ACTIVE being set.
CRs-Fixed: 1017798
Change-Id: Icd62b9d98d5763d209c7de897653f19f8031e236
Signed-off-by: Harry Yang <harryy@codeaurora.org>
When vfe is shutdown vote the bandwidth to 0 otherwise the
higher bandwidth will leak power.
Change-Id: I69e1570fe2bdb2e0b5bc14eb2dc158fe504ce921
CRs-Fixed: 999619
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
ICE 3.0 crypto sequences were changed, CTRL_INFO register
no longer exists and doesn't need to be configured. The configuration
is done via utrd.
Change-Id: I5d69436ec59476fc5cd427458d79f8c99266f243
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
In case of time penalty coming from TZ side when the wrong password
is entered too many times, there should be sleep between the scm calls
to give other HLOS tasks opportunity to run. Otherwise starvation may
occur.
Change-Id: I345a9b6c82fb5e591d8bdcf48afed48ccaafddc3
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
Get deep color support information from sink's EDID (Extended Data
Identification Data). Enable deep color output in hdmi transmitter
if the sink supports RGB 30bpp output format.
CRs-Fixed: 1022772
Change-Id: If65ac051253b4e51f6af5cd60f98eaf908b3bcfd
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add the HDMI Core's device node and its regulators, GPIOs, pin
control and other related data to device tree.
Change-Id: I4373fc9be34d7f49059159256cfd6dca045ff39f
CRs-Fixed: 1022772
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
The HDMI RCGs exported by the MMSS clock controller (MMSS-CC)
can be sourced out of the HDMI PLL which is outside the MMSS-CC.
Set up these external clock sources to point to the HDMI PLL clocks.
CRs-Fixed: 1022772
Change-Id: Ief169f5c456dbdb989788a0147342fe91f0a836f
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
List all the resources needed by the MDSS HDMI PLL device and add
the corresponding device node for msmcobalt. The HDMI PLL is the
source for all the branch clocks needed to drive pixel data over
the HDMI interface.
CRs-Fixed: 1022772
Change-Id: I4cf25e531fea39f7b68bd5ef6edd89243c1ded21
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Add PLL and PHY programming for HDMI. Dynamically calculate
the register values to be programmed for a given pixel clock.
CRs-Fixed: 1022772
Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This change enables the SD card driver support for 8996 boards.
Change-Id: I0e7df68587e1a212e6c2ed7171fcd683cf115604
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add EC reference support for USB audio ADSP solution so that
the USB audio rx can be used for echo cancellation.
Change-Id: If99081c1fd356e69710c94441affec92fac24075
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
This reverts commit 152fc477d3 ("ARM: dts: msm: Add v4l2
rotator node to msm8996").
Smmu attachment failure is reported on v4l2 rotator in devsp.
Revert v4l2 rotator node back to mdss rotator node in devsp
until the smmu issue is resovled.
CRs-Fixed: 1025431
Change-Id: I25a9412c32ddb5d55379b9e96c91f246f6bd4aa9
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Add support for camera flash operation.
Add status property for csiphy, csid camera nodes.
CRs-Fixed: 1021009
Change-Id: Ifa62e4e4662d72904411ff4dda10a29a76962851
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
It's possible thermal driver and governor notify that fmax is being
changed at the same time. In such case we can potentially skip updating
of CPU's capacity. Fix this by updating capacity always when limited
fmax is changed by same entity.
Meanwhile serialize sched_update_cpu_freq_min_max() with spinlock since
this function can be called by multiple drivers at the same time.
Change-Id: I3608cb09c30797bf858f434579fd07555546fb60
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Add the device tree files necessary to support the MSMFALCON
SoC and the MSMFALCON Simulator platform.
Change-Id: Iabdb1c21757ad6dead50fdc4aa3b12077f8f840f
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Enabled BTFM Features in performance defconfig by
default.
Change-Id: I9c007dededd88a7e8bc8c3226507a46046e96bc4
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Enable QPNP_POWER_ON driver for msm-perf_defconfig so that the
input keys can be functional.
CRs-Fixed: 1011669
Change-Id: I9ae7a806a5b659a2c15fa86b37cd1075913095d5
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Time between mark_start of idle task and IRQ handler entry time is CPU
cycle counter stall period. Therefore it's inappropriate to include such
duration as part of sample period when we do frequency estimation.
Fix such suboptimality by replenishing idle task's CPU cycle counter
upon IRQ entry and using irqtime as time delta.
Change-Id: I274d5047a50565cfaaa2fb821ece21c8cf4c991d
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
CPU cycle counter won't increase when CPU or cluster is idle depending
on hardware. Thus using cycle counter in that period of time can
result in incorrect CPU frequency estimation. Use previously calculated
CPU frequency when CPU was idle.
Change-Id: I732b50c974a73c08038995900e008b4e16e9437b
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Preserve cycle counter in rq in preparation for wait time accounting
while CPU idle fix.
Change-Id: I469263c90e12f39bb36bde5ed26298b7c1c77597
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
This change updates the macro definitions to
increase the range on the logs, events and messages.
Change-Id: I8410462b17c5741fb03239377fed18c5f6034b90
CRs-Fixed: 994733
Signed-off-by: Chris Lew <clew@codeaurora.org>
Due to a known PMIC HW bug, hard reset or PR swap may result in
the charger notifying a CC disconnect event in sink mode, in which
case the handler ignores it given these conditions. However, this
closely resembles the case of a non-PD capable source getting
physically disconnected as well. Consisdering the most probable
case of this happening is disconnecting from an SDP while hard
reset was just issued (and will fail), this workaround is currently
racy if repeated plugin/plugout is performed as the timeout to
detect failed hard reset takes a few seconds.
For now, until a HW fix is available, optimize this legacy case
by allowing the disconnect to go through if the detected charger
type is SDP. Also fix the SINK_WAIT_CAP_TIME timeout as it was
incorrectly multiplied by 3 during testing and was not removed.
This will significantly reduce the amount of time for max failed
hard reset attempts for non-PD && non-SDP cases and should decrease
the window for racing with an actual disconnect.
Change-Id: Ic57a369ed1e194ab512b4b86ce4d216df46b5f46
Signed-off-by: Jack Pham <jackp@codeaurora.org>
The user space clients sometimes open the device before the underlying
transport available which results in open error and cause multiple re-tries
from the clients. This leads to excessive logging of open error messages.
Register for link state notification and block the client open until link
available or user define timer expires.
CRs-Fixed: 1018542
Change-Id: I4e56982700f3444f96e1100c0ce272d36d3423a5
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
During parallel migration race conditions are seen in remote open
and local open ack function.
Edge based lock is introduced to avoid any race condition during
simultaneous migration. Edge lock is shared across multiple
transport of same edge and is stored in a global list.
CRs-Fixed: 1010920
Change-Id: I2b988d2a6112add06fa433c4b1deeec0b6e6bb58
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
Add support for gpio keys on msmcobalt CDP and MTP.
CDP and MTP use pmcobalt gpios 6, 7 and 8 for volume up,
camera snapshot and camera focus respectively. CDP
additionally supports home key through pmcobalt gpio 5.
Change-Id: I31f3ed15e8cf02046cfcc8d9c062522065bb022c
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
Use the correct bus governor for Venus VMEM.
Change-Id: I9abc6352732c189e90cefaa3eb4161ea6d103529
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
Update MPM interrupt mapping to bypass some of the interrupts as per the
HW specification.
Change-Id: Ib6f218989616b038adb7a001cbc6302924041aa1
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Adding pm_notify to allow the following:
1. Check if suspend is allowed in an earlier stage to prevent
starting the suspend procedure in case it is not allowed
2. Notify the platform driver on the suspend request
Change-Id: Iddacd9b54304b47263647942e1e6784eefb9a6d2
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: e34dc6475a7b25d1aec5de8652a321672904c686
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
CRs-Fixed: 1015627
Signed-off-by: Maya Erez <merez@codeaurora.org>
In case we fail to map one of the TSO SKB fragments, we need to
clear all the mapped descriptors, from swhead to swhead+descs_used-1.
Change the desc index calculation to
i = (swhead + descs_used - 1) % vring->size;
to prevent unmpping of (swhead + descs_used) descriptor that wasn't
mapped.
Change-Id: I81b99522ada809fa375c6b6887f8ea0e6482fba3
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: a1526f7eafa434f756579e2bc784b7605f96bf3e
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
CRs-Fixed: 1015627
Signed-off-by: Maya Erez <merez@codeaurora.org>
napi_synchronize is called before releasing the vring, with the
assumption that setting txdata->enabled to 0 will prevent handling
of this vring in the next scheduled napi.
To guarantee this assumption, a memory barrier is added after disabling
the txdata.
In addition, as the ctx is zeroed in wil_tx_complete after this
descriptor is handled (protected by wmb), ctx needs to be checked
before releasing this descriptor in wil_vring_free.
Change-Id: I7af20f1db39b7e4c5ac2956fc655f120eb61e002
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: 34b8886e502a62d1355ccc0420044aa2749a24cd
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
CRs-Fixed: 1015627
Signed-off-by: Maya Erez <merez@codeaurora.org>
add memory barrier after allocating new rx descriptors, before
updating the hwtail.
This will guarantee that all writes to descriptors (shared memory)
are done before committing them to HW.
Change-Id: If7c91c31b490b0762d23df21db7c30652b0817d4
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: ab6d7cc3eab4093caf91ba8b27590c4080d7d01c
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
CRs-Fixed: 1015627
Signed-off-by: Maya Erez <merez@codeaurora.org>
There are 2 possible race conditions, both are solved by addition of
memory barrier:
1. wil_tx_complete reads the swhead to determine if the vring is
empty. In case the swhead was updated before the descriptor update
was performed in __wil_tx_vring/__wil_tx_vring_tso, the completion
loop will not end and as the DU bit may still be set from a previous
run, this skb can be handled as completed before it was sent, which
will lead to double free of the same SKB.
2. __wil_tx_vring/__wil_tx_vring_tso calculate the number of available
descriptors according to the swtail. In case the swtail is updated
before memset of ctx to zero is completed, we can handle this
descriptor while later on ctx is zeroed.
Change-Id: Ia6584de897c366032251033aa8e03c54e9d899bb
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Git-commit: eb26cff148f5449972121e46e403f549d71f6f49
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
CRs-Fixed: 1015627
Signed-off-by: Maya Erez <merez@codeaurora.org>
Currently burst value is set to zero for superspeed in mtp driver.
MTP throughput can be improved by setting max burst value to non
zero value in superspeed mode. Hence set max burst value to two
for both IN and OUT bulk endpoints in superspeed mode.
Change-Id: Ib78b8fec5d1ab934f4d4ec80b7e008149707ce0f
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Convert print messages to IPC logging facilities. This
will allow for easier debugging from crash dumps as
well as from debugfs. The print calls are converted to
macros which also print to the console for flexibility.
Change-Id: I6238b0434936fcff562d7a049e5e9d13794f9cdc
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Some platforms might not support auto hibern8 even though the
controller exposes this capability. Add a quirk to disable
auto hibern8 for such platforms.
Change-Id: I4a027f89deddff4735df45da9cffbfb1849af5f4
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This patch fixes the possible corruption of the
dci client entries log mask during deinit of dci
entries.
CRs-Fixed: 1021816
Change-Id: I7741eca6ac07cd4393fc373e796570066da7cce6
Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
Make turbo voting threshold lower to 1000Mbps to account for CPE
use case.
Change-Id: I5d02d3df7b69e30243a0b44ddf36a894ad739d59
CRs-Fixed: 872263
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
QCOM UFS host controller v3.0.0 supports hw gating of clocks, use
the hw ctl clock variants of ufs clocks to enable that support.
Change-Id: I9597507419e59884c44429c8c34f7469fa5192cb
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
QCOM UFS host controller v3.0.0 supports running at much lower
frequencies that allow SVS2. Update the UFS clock supported
table with new min frequencies.
Change-Id: I11d941f239ccd1978089194fa269e143fc640d36
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
