* refs/heads/tmp-482cc74
Linux 4.4.100
USB: serial: garmin_gps: fix memory leak on probe errors
USB: serial: garmin_gps: fix I/O after failed probe and remove
USB: serial: qcserial: add pid/vid for Sierra Wireless EM7355 fw update
USB: Add delay-init quirk for Corsair K70 LUX keyboards
USB: usbfs: compute urb->actual_length for isochronous
uapi: fix linux/rds.h userspace compilation errors
uapi: fix linux/rds.h userspace compilation error
Revert "uapi: fix linux/rds.h userspace compilation errors"
Revert "crypto: xts - Add ECB dependency"
MIPS: Netlogic: Exclude netlogic,xlp-pic code from XLR builds
MIPS: init: Ensure reserved memory regions are not added to bootmem
MIPS: init: Ensure bootmem does not corrupt reserved memory
mm: add PHYS_PFN, use it in __phys_to_pfn()
MIPS: End asm function prologue macros with .insn
staging: rtl8712: fixed little endian problem
ixgbe: do not disable FEC from the driver
ixgbe: add mask for 64 RSS queues
ixgbe: Reduce I2C retry count on X550 devices
ixgbe: handle close/suspend race with netif_device_detach/present
ixgbe: fix AER error handling
arm64: dts: NS2: reserve memory for Nitro firmware
ALSA: hda/realtek - Add new codec ID ALC299
gpu: drm: mgag200: mgag200_main:- Handle error from pci_iomap
backlight: adp5520: Fix error handling in adp5520_bl_probe()
backlight: lcd: Fix race condition during register
ALSA: vx: Fix possible transfer overflow
ALSA: vx: Don't try to update capture stream before running
scsi: lpfc: Clear the VendorVersion in the PLOGI/PLOGI ACC payload
scsi: lpfc: Correct issue leading to oops during link reset
scsi: lpfc: Correct host name in symbolic_name field
scsi: lpfc: FCoE VPort enable-disable does not bring up the VPort
scsi: lpfc: Add missing memory barrier
staging: rtl8188eu: fix incorrect ERROR tags from logs
scsi: ufs: add capability to keep auto bkops always enabled
scsi: ufs-qcom: Fix module autoload
igb: Fix hw_dbg logging in igb_update_flash_i210
igb: close/suspend race in netif_device_detach
igb: reset the PHY before reading the PHY ID
drm/sti: sti_vtg: Handle return NULL error from devm_ioremap_nocache
ata: SATA_MV should depend on HAS_DMA
ata: SATA_HIGHBANK should depend on HAS_DMA
ata: ATA_BMDMA should depend on HAS_DMA
ARM: dts: Fix omap3 off mode pull defines
ARM: OMAP2+: Fix init for multiple quirks for the same SoC
ARM: dts: Fix am335x and dm814x scm syscon to probe children
ARM: dts: Fix compatible for ti81xx uarts for 8250
fm10k: request reset when mbx->state changes
extcon: palmas: Check the parent instance to prevent the NULL
dmaengine: dmatest: warn user when dma test times out
Bluetooth: btusb: fix QCA Rome suspend/resume
arm: crypto: reduce priority of bit-sliced AES cipher
net: qmi_wwan: fix divide by 0 on bad descriptors
net: cdc_ether: fix divide by 0 on bad descriptors
sctp: do not peel off an assoc from one netns to another one
xen-blkback: don't leak stack data via response ring
bpf: don't let ldimm64 leak map addresses on unprivileged
KVM: x86: fix singlestepping over syscall
ext4: fix data exposure after a crash
media: dib0700: fix invalid dvb_detach argument
media: imon: Fix null-ptr-deref in imon_probe
BACKPORT: arm64: Use __pa_symbol for empty_zero_page
BACKPORT: arm64: Use __pa_symbol for kernel symbols
UPSTREAM: mm: Introduce lm_alias
Conflicts:
arch/arm64/kernel/insn.c
arch/arm64/kernel/setup.c
arch/arm64/mm/mmu.c
drivers/scsi/ufs/ufshcd.h
Change-Id: I4ffc41779ec115eecab09d72dd8042151514be39
Signed-off-by: Srinivasarao P <spathi@codeaurora.org>
[ Upstream commit d97556c8012015901a3ce77f46960078139cd79d ]
We need to also have OFFPULLUDENABLE bit set to use the off mode pull values.
Otherwise the line is pulled down internally if no external pull exists.
This is has some documentation at:
http://processors.wiki.ti.com/index.php/Optimizing_OMAP35x_and_AM/DM37x_OFF_mode_PAD_configuration
Note that the value is still glitchy during off mode transitions as documented
in spz319f.pdf "Advisory 1.45". It's best to use external pulls instead of
relying on the internal ones for off mode and even then anything pulled up
will get driven down momentarily on off mode restore for GPIO banks other
than bank1.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The max20010 external buck supplies VDD_GFX for msm8996-auto
boards. Add max20010 regulator device driver to program the
necessary configuration as per the board specific requirements.
CRs-Fixed: 2062515
Change-Id: I68ad73e0c7cff1a87d218dc4677801f9e0206db6
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
The MND values and the PLL output divider configuration does
not match the recommended values. When setting DSI pixel clock
rate the MND array is ordered in a way that the requested
rate goes from highest to lowest. Since the recommendation is
to divide the clocks as close to VCO as possible, the request
should be from lowest to highest. So reversing the fraction
array to match the recommendation. The VCO min max rates are
currently forced after pll output divider which is also fixed.
Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Add the pinctrl clock for ln_bb_clk to the GCC driver
for MSM8996.
CRs-Fixed: 1063062
Change-Id: If85a0dbb26e350588cbd6614c032bf208a205be2
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Add DVDD_HARD_RESET and DVDD_SHUTDOWN types to power-on.h so that
they can be used in PMIC PON configuration.
CRs-Fixed: 2017642
Change-Id: I34ec58230fe38a193c50f7bf4d3ab0b2d96f82f1
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Separate out the aggre2_noc voters so that individual voters could vote on
these clocks and voter clock would aggregate the clock rates before sending
a request to RPM.
Change-Id: I8ef30af257d2f37ec5af6aa5e3d1b69e5ba8ec8c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The gcc_hmss_ahb_clk will be controlled by RPM. Remove all
control of it from the HLOS clock driver.
Change-Id: I26525787352cb0b85937cc005afba7c37a7989ff
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Following list of changes have been made
1. Add the missing clocks in multimedia clock controller driver.
Also clean up clock flags and parent info for few clocks.
2. Removing clocks which are not controlled by HLOS.
3. MMCC needs to vote for volatge level on rail for the clock
frequencies, so add voltage voting in MMCC.
4. Initial rate configuration for MMPLLs.
Change-Id: If3d84e52783651b611b624dbc60b18993c0f0b1a
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
The gcc_hmss_ahb_clk will be controlled by RPM. Remove all
control of it from the Linux clock driver.
Change-Id: I0a6885e286841eb3f2d31223da3d430dde21d975
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The gcc_rx2_qlink_clkref_clk is not required by
any client, so remove controlling the clock from
HLOS clock driver.
Change-Id: I20dbb38f3f0fcbcdb3974923f4a0b540153d3fde
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Model and configure MDSS Display Port PLL for SDM660 target.
Add changes to define and register DP VCO, divider and mux clocks
as per common clock infrastructure.
Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Add parents to div_clk1 and ln_bbclk. And register
both the clocks independently.
Change-Id: Ic0435ebad533879e3e0648775956c91cc680644d
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need
to left at their default state of ON. Remove controlling them
from the linux clock driver to avoid disabling them during
late_init.
Change-Id: Iefc033998bf87fcc98dfaa1b7321d9cc33dedd5e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
CPU clocks would require to vote on active only instance of GPLL0, so add
the clock and also update the parent names for the CPU clocks.
Change-Id: Id8c7f76170a1cc94fe045b8ba975aaa42c4b3819
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GPU RBCPR clocks needs to registered separately, as GFX CPR would require
the rbcpr clocks to register the regulator handle.
Change-Id: I59def76e7dd69600be8faf47eb867a97ab04739e
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Following are the changes made:
1. Add CLK_IGNORE_UNUSED flag for some clocks which are not
supposed to be disabled at late_init_level.
2. Fix clock measure debug mux value for mmcc clocks.
3. Add mmss_mdss_byte1_intf_div_clk for mdp.
4. Fix usb ref clocks to branch voted.
Change-Id: I06396c73f7855acfac283abe576e0b4cc1a92bd5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".
Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
MSM8996 requires the voter & voter branch clocks to be
available for clients to be able to enable/disable and
set rate on these clocks.
Also add support for keeping active set vote on mmssnoc
and pnoc voter clocks.
Change-Id: Ie596ddee60aac3e6fc996f9a3e8dc988b0f4aa88
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Global Clock Controller(GCC) needs to vote for volatge level on
rail for the clock frequencies, so add voltage voting in GCC.
Also clean up clock flags and parent info for few clocks.
Change-Id: Ib4cc69afb32a7654bbdd98f2efff901729c4d3da
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Following list of changes have been made
- Update the clock osm to register to common clock framework
- Update clock ops as per common clock framework
- cleanup unused function (clk_osm_setup_osm_was)
- Fix tabs for macro definitions
- Add clocks ids for power and perf clock for clients
Change-Id: I389cc9e93a26a434be752cf74444d6c0985ff36d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add new voter clocks of camss_jpeg0 clocks which are required by camera
client. Update the clock indexes for multimedia clocks for the same. Also
update the clock ops for hardware control branch clocks.
Change-Id: I4bc6608789b8b900e0af007d2ca24ba19f675cb7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add new bus master id to identify the pimem bus master
for bandwidth aggregation and QoS programming done
by the bus driver.
Change-Id: I0991065984b35511c33ab4c9bd274ad465d19601
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Model and configure MDSS DSI PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clcoks
as per common clock infrastructure.
Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
In order to avoid leakage between the graphics and the CX
rails, set the GPU_DD_WRAP_CTRL__GFX_PDN bit.
Change-Id: I7b2e59606e73c467c2b862f0162a176611d7ae3d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
As audio-ext-clk.h is finally included in device tree and
and using ifdef results in compilation failure. Delete
ifdef from audio-ext-clk.h.
CRs-Fixed: 1090500
Change-Id: Ib6f715c3f606770e7e0b1f0f84ab50e442398cd0
Signed-off-by: Meng Wang <mwang@codeaurora.org>
Update the code name from msmcobalt to msm8998. As a result, update
the filename containing "cobalt" and files content containing "cobalt".
CRs-Fixed: 1070840
Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Add support for the multimedia clock controller found on MSMFalcon
based devices. This should allow most clocks for multimedia peripherals
which includes display, video, camera etc.
Change-Id: If8aa0b094af5ff82fe66c95e3ef2f13632950d2e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add clock of_idx entries for audio external clock registered
to the qcom clock framework.
Change-Id: Ie592d06d2e09c2e263a2e9485a42eafb368e49cc
Signed-off-by: Meng Wang <mwang@codeaurora.org>
The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need
to left at their default state of ON. Remove controlling them
from the linux clock driver to avoid disabling them during
late_init.
Change-Id: If3d964840362b6147ba7c9e26c4a3f5d20e5a557
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The turing hlos1 and hlos2 vote clocks is required to be enabled before
accessing the turing SMMUs, so add support for the same.
Change-Id: I9e4b0d7cc5f164b207a1a0e2c1ae24bdfd8fa063
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The post vco divider clock in the DSI PLL can only be configured
to a fixed value of 1 or 4. Current implementation can result in
the divider being set to any value between 1 and 4 which can
result in failures while enabling the DSI pixel clock. Fix this
by replacing the post vco divider with a fixed /1 and /4 dividers
followed by a mux clock.
CRs-Fixed: 1064277
Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support for the graphics clock controller found on MSMFalcon based
devices. This should allow graphics clocks for GFX clients to be able to do
clock functionality.
Change-Id: I753b40d574a4afc2104a5c2bfe64b4831fbce8a0
Signed-off-by: Taniya Das <tdas@codeaurora.org>
For MSMfalcon and MSMtriton, clock consumers requires dummy
rpmcc, gcc, mmss and gfx clocks for their operation so add
the support for registering dummy clocks as follows:
- Add clock-output-names property for the rpmcc, gcc, mmss
and gfx clock controller nodes.
- Add reset-cells property for clock controller nodes.
- Add two fixed clock nodes named as xo_board and sleep_clk.
- Remove RPM clock IDs from qcom,gcc-msmfalcon.h.
- Modify RPM clock names as per qcom,rpmcc.h file.
Change-Id: I06262fe271ab6ba81d4fa5f67315fd1b54edee8c
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
