CPU write buffer must be flushed before a DMA operation
is signaled to the device.
CRs-Fixed: 812602
Change-Id: I304671fd1a403d6d897b47641910bc112310b674
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable M2 power state transition exit through
CLKREQ GPIO assertion due to MHI doorbell write.
CRs-Fixed: 733370
Change-Id: I27b425ee305fc9c044812a8b15c76970987a5dae
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable NER support for MHI core. MHI core now enables
only event rings required for used channels. This saves
a substantial amount of system memory.
Change-Id: I3b9d63875cf117fba2ac062f831da1899b355e2c
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable log level sysfs attribute for MHI UCI
to enable different verbosity levels at runtime to the IPC log.
CRs-Fixed: 734010
Change-Id: I866b5bebb08257ac120de565a7b2a83b8e831a1a
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Remove dead code from the MHI driver. Currently there is no
usecase for the MHI STOP and NOP commands and this codepath is not
being touched.
Change-Id: I6cd96e28b9f46aca8014bbe4d2f2aa701f40b08b
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable large buffer sizes for SAHARA to reduce number
of data transfers by a factor of 12.
CRs-Fixed: 800039
Change-Id: Ica59ae4e3eae3b7c64222d36a8bc5033928ae631
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Flush pending PCIe writes after setting D3 hot and after
setting M2. This will ensure that no writes will bring the link
down as it is being turned off.
CRs-Fixed: 755658
Change-Id: If2ca4575f833ede77d6a14e1e2bf5a86d1c28218
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable queue TRE function for treating both command and transfer
TREs in the same codepath. This simplifies the flow of processing TREs
and facilitates debugging.
Change-Id: I8dc1dec4e0e23b7b36982cc0ace957a1b43aa6da
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Currently on UCI open, if the transport is not ready, the open
is succeeded in hopes that the transport becomes ready in the future.
Increase transparency between UCI clients and MHI such that
when the transport is not ready the UCI client is notified
and can react accordingly.
Change-Id: Iacc85e9aa68be9cde152a3fc2bfe9d0c6f6f6b62
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Assert when an event is received for a channel which is empty.
This is a fatal transport error.
Change-Id: I0249f97480ebc3ca8d3e98c10e35a0eb040215a4
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
This reverts commit e38c1ec36984945d60d02002eae5e615d1b9b6aa.
This commit can generate a link down in M2 state where the doorbell
is flushed while the link is down.
Change-Id: If29db648f0c6d2b0bd7a3d3a9b0f31ae5512c4eb
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable runtime PM in the MHI driver to increase transparency
between kernel and device driver and synchronize runtime PM
actions with system wide power states.
Change-Id: I8b87c2ed7b0be8a4cf9568ac1fb772eebe416dc6
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Ring out pending doorbells in the event of a cancelled M3 transition
attempt.
Change-Id: I83ffe0407618ea26768707fc6341d20947ef3ba2
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
When the netdev interface is released, NAPI is disabled.
This condition can occur while the device is still sending RX data
causing a potential kernel panic.
Wait for all incoming data to be received, before releasing
the interface.
Change-Id: If33ff721a581fdafb9712fe3cf9243996187f09d
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
MHI RmNet will now wait for all packet fragments from MHI before
sending the received packet up the network stack.
Change-Id: I3f0958d029a5763e7e0b1e4ab43f17fd98583a48
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Reduce interrupt moderation for both inbound and outbound
hardware channels to 1ms, for improved latency response to
device acknowledgements.
CRs-Fixed: 782801
Change-Id: Id0717582d88dcfc12a8711f983da59a8f651b6d3
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable support for NER as part of the MHI REV E
specification. NER register will now be set to the
maximum number of channels supported by MHI.
Change-Id: Id868c04886af13cd34720c86a55ac64debc4ab31
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Prevent event counter from getting incremented twice and breaking
the modulo operation.
Change-Id: I472115a3d65a84904482455d00cee9de6d31043b
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Resolve a race condition whereby a buffer could be freed
by the SSR handler while being operated upon by the transfer
callback.
Change-Id: I5e62b04166b2a8a9867047574c7232739229c911
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
A race condition exists in MHI_UCI whereby a client could receive
a buffer, inconsistent with the return code from MHI.
Change-Id: I4a932ea608ce967c1588f092c60d03747bad2064
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable ftrace events in MHI for the tracing of power
state transitions.
Change-Id: I74373b7429c6d7316c4a66db141cc09e2a4418dd
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
The pending TRE iterator is not properly initialized
and checked against, leading to an incorrect number of
TREs getting processed.
CRs-Fixed: 748475
Change-Id: Ie8609edd1a89d8dc14bf781612357d7dc524f83a
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enabled sanity check for LPM IOCTL in MHI. IOCTL should not
be called into MHI, if the device is not ready.
CRs-Fixed: 749894
Change-Id: I52627a94e70e3b17130653b7b73a86b417807842
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Reorder operations on MHI TRE to prevent a race condition
of publishing the TRE to the device before the TRE is fully
populated.
CRs-Fixed: 726655
Change-Id: Ide208c77c93f0e68eee0c6c304eaebc451028341
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
The doorbell value for the event ring must be sampled within
spinlock context or the value could be stale when written.
CRs-Fixed: 746401
Change-Id: I4eb5095f34b890e02fee48c22206afcbfd70a454
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
A timing window exists where M3 state transition is pending and
the doorbell does not get written out. The M3 process is then
cancelled, and no M0 event takes place to flush the doorbell out.
Remove setting the pending M3 flag until the transition is no
longer cancelable.
CRs-Fixed: 733632
Change-Id: I3b4dfe23d0ea4af69d2810a171c61dc60a6c2f8d
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enabled event ring context updates regardless of MHI
power state.
Change-Id: I910d056d53f7c940caea48546c206d4603e8a4b9
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
After a channel reset, any pending acks on that channel
will not be received from the device.
In this case they must be cleared in the channel reset
command handling.
CRs-Fixed: 733172
Change-Id: I5b7c525f7f532ed107caa020cde33ec1955ae618
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Resolve issue whereby a deadblock is encountered when trying
to put the interface down.
Change-Id: I757492fceff56014b28ec50307f6d84b1bb81889
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Fixed a race condition in MHI RmNet where the RX interrupt
could remain masked forever.
CRs-Fixed: 723355
Change-Id: I9606963b8b2d6d1cb125c0bc7be8610b06f67be3
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Fix race condition in MHI RmNet whereby the outbound
MHI ring could be empty while the network stack believes
it is full. This leads to a non recoverable data stall.
Add rwlock to ensure checks for full and empty conditions
are atomic.
CRs-Fixed: 733646
Change-Id: If54baa4be762a976d64213d0ec52e969f2497036
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Reset the pending packets counter in UCI when a client releases
the character device node.
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Change-Id: Ic3d83873ae207e76acbb9f60683b43cb30ff7c5b
Resolve issue regarding BHI image load process.
Interface will no longer be published to userspace
before local initialization is complete.
Register masks and retry mechanism are also cleaned up.
Change-Id: I05d87d4be5e9c05c6beb2b7b0c0234757b93097d
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Add the msmzirc device in the list of supported PCI devices
by the MHI driver to enable to PCIe framework to probe MHI
in the event of discovering this device on the bus.
CRs-Fixed: 736039
Change-Id: I66eb5f67885d60c579c33c47ce696d66c6c428b5
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Remove the incorrect direct de-reference of device mapped
IO mememory and replace with kernel standard handlers.
CRs-Fixed: 728285
Change-Id: I0b3afe8a62369057b4a6b45b1a71bd9f5a52ce1d
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Enable the MHI core driver for communication
between host and device using PCIe as an interconnect
and supporting MHI as the communication protocol.
The driver exposes several kernel space APIs
for use by other kernel entities to interface to
the PCIe device over MHI.
APIs for read and write and other notifications
are supported by this MHI driver.
Support for full power management and device reset
is also included.
CRs-Fixed: 689329
Change-Id: Ibc2fd7c2d5689001485f71b1133ada2c4ca236a9
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
Add MHI RmNet driver to support exposure of an
MHI device as a network interface to the Linux
networking stack.
The MHI channels are exposed as a standard network
interface which supports the NAPI framework.
IOCTLs for setting MTU/MRU and LPM are also enabled.
CRs-Fixed: 689329
Change-Id: I9540c78acccec35aff4ee4dc36241c6f08cdf04c
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
The MHI UCI driver exposes MHI core functionality to
userspace by means of device nodes.
The UCI driver exposes a device node for a pair of unidirectional
MHI channels.
The supported system calls on the device nodes are read, write,
select/poll and RS232 IOCTLs.
CRs-Fixed: 689329
Change-Id: Iceab97dba7c3bbb4eb7bf0c4ab0c1eac8c5417e9
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
When a deferrable work (INIT_DEFERRABLE_WORK, etc.) is queued via
queue_delayed_work() it's probably intended to run the work item on any
CPU that isn't idle. However, we queue the work to run at a later time
by starting a deferrable timer that binds to whatever CPU the work is
queued on which is same with queue_delayed_work_on(smp_processor_id())
effectively.
As a result WORK_CPU_UNBOUND work items aren't really cpu unbound now.
In fact this is perfectly fine with UP kernel and also won't affect much a
system without dyntick with SMP kernel too as every cpus run timers
periodically. But on SMP systems with dyntick current implementation leads
deferrable timers not very scalable because the timer's base which has
queued the deferrable timer won't wake up till next non-deferrable timer
expires even though there are possible other non idle cpus are running
which are able to run expired deferrable timers.
The deferrable work is a good example of the current implementation's
victim like below.
INIT_DEFERRABLE_WORK(&dwork, fn);
CPU 0 CPU 1
queue_delayed_work(wq, &dwork, HZ);
queue_delayed_work_on(WORK_CPU_UNBOUND);
...
__mod_timer() -> queues timer to the
current cpu's timer
base.
...
tick_nohz_idle_enter() -> cpu enters idle.
A second later
cpu 0 is now in idle. cpu 1 exits idle or wasn't in idle so
now it's in active but won't
cpu 0 won't wake up till next handle cpu unbound deferrable timer
non-deferrable timer expires. as it's in cpu 0's timer base.
To make all cpu unbound deferrable timers are scalable, introduce a common
timer base which is only for cpu unbound deferrable timers to make those
are indeed cpu unbound so that can be scheduled by tick_do_timer_cpu.
This common timer fixes scalability issue of delayed work and all other cpu
unbound deferrable timer using implementations.
Change-Id: I8b6c57d8b6445a76fa02a8cb598a8ef22aef7200
CC: Thomas Gleixner <tglx@linutronix.de>
CC: John Stultz <john.stultz@linaro.org>
CC: Tejun Heo <tj@kernel.org>
[joonwoop@codeaurora.org: timer->base replaced with CPU index so get
the deferrable timer wheel from lock_timer_base() instead of
do_init_timer().]
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
ADSP Loader is required for the audio probes and memlat governor
is crashing right now so we should keep it disabled for now.
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Different kernel version needs to use different kernel APIs for
hotplug. Add wrapper for CPU hotplug so that external module can be
used across different kernel releases.
Use device_online/offline() API for CPU hotplug.
Change-Id: Id21855f4ddc62bc9e9e6b45a856c245fd18d1514
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Some applications still include android_pmem.h although all the
functionality for it is gone from the kernel. Keep this header
file around until all such users have removed the include.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[satyap: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
