For TX5 MUX registers, offset is not followed
in TXn order. Update driver to read/write correct
register offset when TX5 MUX registers access.
CRs-Fixed: 2218938
Change-Id: I8958b6cd1847967cbd37e7145c9f3909b0b8853b
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
If soundcard registration has failed because of custom
driver probe failure and at the same time
msm_dig_suspend is called, this will lead to
null pointer dereference when component is accessed.
Add NULL check to avoid this.
CRs-Fixed: 2263093
Change-Id: I2d321814a316d9b3af1ff0f8963f2999520e60d2
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
When AFE returns failure in setting the digital codec
core clock during SSR, it leads to LPASS register access
which results in NOC error and AHB timeout. Put the regmap
in cache only mode when clock enable fails to fix this.
Also fix watchdog bite failure during stability run
by returning from digclock control if cacheonly mode
is set. This is seen while SSR is in progress and teardown
of session happens, it will request for afe clock enable
continuously at digital clock control.
Change-Id: I952b667a5cffcb667154378102609b23ab0cee3d
Signed-off-by: Soumya Managoli <smanag@codeaurora.org>
Pop is observed during switch from playback in native mode
to voice call and vice-versa. This is resolved by mclk
reset to non-native mode before hph path powers up.
CRs-Fixed: 2117960
Change-Id: I53d5f985453895d34179610e3a414021eade7bcb
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
Pop noise occurs during switch from handset to speaker mode
during voice call. This is because sufficient delay
is not provided for tx to unmute. A delayed workqueue
that will do unmute at the end solves the issue.
CRs-Fixed: 2101423
Change-Id: Idc1fd8e770eb0d361bd436ce35940200173106ef
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
Pop is observed after we start playback on hph.
This is because we do not enable both compander
channels at the same time which is not according to
qcrg. Amplitude of pop gets reduced after
corresponding change is made.
Also kernel panic is observed during SSR. This is because
DSP does not get sufficient time to bring up LPASS after SSR.
An increase in ADSP Ready timeout resolves the issue.
CRs-Fixed: 2101404
Change-Id: Iaea0f5060cdd87754e074ecbba18b5045cd4351a
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
Compander disable sequence does not get called
after headphone playback on fm. This results in
mute at one channel and low volume at other channel.
Low volume is resolved by setting analog mode to manual
while compander is off.
Also compander clock should be disabled at the end to
resolve mute issue.
CRs-Fixed: 2102126
Change-Id: I68e72f3b333117a8fdf379db30dc24de9bed7270
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
Add Writeable registers list for Digital codec and soundwire codec
regmap config to avoid invalid register access during reg_cache_sync.
Ensure digital codec clock is enabled before regcache sync to avoid
AHB access errors.Modify mutex use to avoid clock disabling during
regmap register access.
Change-Id: I8ab84f80298e01d145395f1347352afe5cfbcc9e
Signed-off-by: Ramprasad Katkam <katkam@codeaurora.org>
In particular SSR scenario, digital codec access happens without
clock enabled. While SSR down event notification in progress,
APR driver blocks request to DSP to enable clock since APR already
received down event. regmap access to digital codec register results in
AHB timeout error. If DSP clock enable request fails, set the regmap
access cache only mode to avoid any register access.
CRs-Fixed: 2034468
Change-Id: Id1141339d2673920167ed7ac74b13b6fee05173f
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Widget suspend is not ignored since stream names mismatch.
Correct stream names and add dapm sync for widgets to work during
suspend. Order of digital PM suspend and soc codec suspend differs,
which results in mclk remaining on during suspend, so change
digital PM suspend to late suspend.
Change-Id: I37d64b044714847cee70a83df9480fbccbf6efc5
Signed-off-by: Divya Ojha <dojha@codeaurora.org>
Enable digital clock bits before digital codec reset.
Also update HD2 settings as per latest HW sequences.
CRs-Fixed: 2018603
Change-Id: I270a324ffebc8b84ef23ff6b209efcde724f9b37
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
ADIE RTAC register parsing logic expects the registers value to
be 1 byte for all the codecs.Change the val_bits in regmap
config structure of the digital codec to 8 bits from 32 bits.
CRs-fixed: 2014589
Change-Id: Ib7a022c420cbd27aeac75ac061f96f8a1f39bd2e
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Add support for 192k/96k sampling rates for HPH RX
on SDM660 internal codec.
Change-Id: I364cdfc1b3e086158b6d115b7e4c4ddaf5c132b1
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
In digital codec, null codec pointer access can happen
in suspend call if module register happen with pm_ops
but soc codec register failed for some reason. Add null
check in msm_dig_suspend API to avoid crash scenarios.
Change-Id: I15acb69a1851b7865d2b3aa1b7cb70a4a73c63e3
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Digital codec soc suspend enables mclk, preventing XO shutdown.
So implement digital codec pm suspend to disable mclk. Add ignore
suspend property to new widgets to resolve powering up and down
during suspend.
Change-Id: I2a773cdfe25d408d95f1c07be71fd4be740e8bf0
Signed-off-by: Divya Ojha <dojha@codeaurora.org>
In SDM660 internal codec drivers, both platform dev probe and
snd_soc codec probe allocate different structures but
update allocated address pointer to same driver data info.
This causes override of earlier structure location.
Combine the structures to make single codec private data.
CRs-Fixed: 2012230, 2013959
Change-Id: I6c6c43f408fb00003ca43d78919f54ba87f37ffd
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
For internal codec SSR, remove regcache sync as
regcache operations over SPMI is not supported.
Enable SSR for both internal codec and WSA codec.
CRs-Fixed: 2001499
Change-Id: I98c363c45973d50654af231d5a7772ba059fccac
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Update module names of ADIE RTAC for digital and
analog codecs. And update machine driver to
update codec_root of pdata.
Change-Id: Id5c2367a2aac31e80cc0a37f72160b73c7adcdde
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Add route map and mix controls to support 4 digital mics
in SDM660 internal codec.
Change-Id: Ida16a910961d01a57d7d03dd64b61ecd36bad37d
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Update internal codec settings for RX/TX devices.
Disable lpass notifier in analog codec driver.
Handle 44.1K support in machine driver to
disable MCLK before request for change in
MCLK frequency.
Change-Id: I5f78f07da46dee0c66e4e374da600e2e5c5d8e21
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".
Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
2016-12-28 21:56:21 +05:30
Renamed from sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c (Browse further)
