SDA660 HDK platform has DP hardware blocks, so enable it in the
device tree.
CRs-Fixed: 2064346
Change-Id: Ieb524e37ed2f4cdd5776759b00ec182378ff6ff5
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
Make use of mutex lock to access IOCTL so that two threads
can avoid race condition.
Change-Id: I00db78a42c86eef8a157b5b3547e4ca0006b0853
Signed-off-by: annamraj <annamraj@codeaurora.org>
The current vote mapping is not sufficient for the most of the
gaming usecases on sdm630. Added intermediate voting in the
current mapping.
CRs-Fixed: 2033301
Change-Id: Ie376a3ce46ccfd31a067dfa93967bb211e9df97a
Signed-off-by: Prasanth Kamuju <pkamuju@codeaurora.org>
Add qseecom device node in guest VM configuration.
This commit adds the device node for the qseecom driver,
and also the reserved memory region for the QSEECOM ION heap.
Change-Id: Ibdf80d080208b5ab8530a1c40ecbccc7298ae89b
Signed-off-by: Amit Blay <ablay@codeaurora.org>
Copying the flash initialization parameters from userspace memory to
kernel memory and in turn checking for the validity of the flash
initialization parameters pointer sent from userspace
Change-Id: I9ecd0a5d320a68ef23fb8dd0d4eaab7f7da5f729
CR fixed: 2059812
Signed-off-by: Rahul Sharma <sharah@codeaurora.org>
Signed-off-by: Andy Sun <bins@codeaurora.org>
During qseecom driver probing, the ION driver is invoked.
This commit supports the case where the ION driver still hasn't
probed. In that case, the qseecom probing will be deferred, and
retried at a later stage.
Change-Id: Ic780e8fa1d48a9f5b8b98773c034b280475f5fd0
Signed-off-by: Amit Blay <ablay@codeaurora.org>
The size of the settings, copied from userspace, is directly checked
in msm_cci_data_queue with CCI_I2C_MAX_WRITE. This might cause
out of bound access in function msm_cci_data_queue as the max size is
MAX_I2C_REG_SET. Hence adding check on the size in flash driver itself.
Change-Id: Iaf8b62815282386af58d1b111876cc80411385a0
CR fixed: 2062894
Signed-off-by: Rahul Sharma <sharah@codeaurora.org>
Signed-off-by: Andy Sun <bins@codeaurora.org>
On A5XX GPU hardware clock gating needs to be turned off before
reading certain GPU registers via AHB. Turn off HWCG before calling
adreno_show() to safely dump all the registers without a system hang.
Change-Id: Ic0dedbad550ab5d414cea7837672e586a7acd370
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Remember if the A5XX hardware clock gating is currently
enabled or disabled to avoid inadvertently enabling it.
Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enabling and disabling the power at various points in the ->show()
call flow may have detrimental effects. For all targets make sure
power is on before reading any register and leave it on until we are
all done.
Change-Id: Ic0dedbad4d37a11634174105fc3ee6fe3713a143
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The generic msm_gpu_pm_resume/msm_gpu_pm_suspend functions have
built-in reference counting but the a5xx specific functions
are doing unconditional a5xx specific setup / teardown that
would behave very badly if they were not accompanied by an
actual power up / power down.
Change-Id: Ic0dedbad549c4ea9a5c68b0ca43eb98e0449d54b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Immediately deinit MHI after powerup failure will clear all the
MHI context so it won't be able to enter RDDM state to collect
firmware RAM dump. Leave the cleanup to SSR shutdown routine.
Change-Id: Ibbbe3ffe3c471f69dd4fc89d7cfaf57f1f899a92
CRs-fixed: 2059087
Signed-off-by: Yue Ma <yuem@codeaurora.org>
